LDMOD SD57060 gate voltage issue
i am using SD57060 LDMOS for 850MHz TO 870MHz band.
The amplifier specs are
Vdd 28v
vgs 2.67v @idq = 100mA
input power = 1.9watts.
amplifier gain 12db approax
output power 20 watts.
The amplifier circuit/matching is designed using ADS momentum simulation.
So far i have damaged 3 LDMOS during testing. The amplifier is always terminated
with dummy load or matched antenna during power up. After sometime or after on/off power supply the vgs (gate to source) voltage disappears and voltmeter read 0 volt. Gate to source shows 10-25 ohm resistance.Amplifier still works but the reason for damage is still unknown. Is there any transient in power supply which is causing
the damage.
Do you have a filter on supply gate? Can you show schematic circuit?
Maybe, you can have spurious feedback.
first things I would check are:
1) is the fet adequately heat sunk?
2) is there a chance the fet is oscillating at low frequency (like 10 MHz) and wiping itself out. Did you do a wideband stability analysis. I see a lot of funky things designed into LDMOS bias networks to kill low frequency oscillations.
If voltmeter is always connected betweeen Gate-Source, your amplifier may oscillate and this destroys the transistor.
Use a 100K resistor in series to Gate and connect your voltmeter via a seperate testpoint for that..
Thanks for reply.
I am using the biasing network which is given in SD57060 datasheet.
LDMOS is mounted on heat sink.
I want to ask question about amplifier stability. Suppose, ADS large scale S-Parameter simulation gives stability factor (k<1) at the desired frequency band. Amplifier can be stabilize by adding series resistors at the gate side. Is it possible to stabilize the amplifier by designing input/output matching network and leaving adding series resistor?