how to select Dielectric Resonator for designing DRO?
时间:04-04
整理:3721RD
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I have been designing PLL circuits using VCOs to generate carrier frequencies close to 4GHz.
The VCOs come with wide tuning range,but quite bad close-in phase noise.
My application demands,best possible phase noise,atleast an improvement of 10 folds over
VCO based PLL.
I looked for options, and found that DRO based carrier generation has potential to do so.
Being very new to this area,I wish to take help of forum members,while selecting an appropriate
dielectric resonator for designing a DRO to generate frequencies close to 4GHz.
My design specs are something like this:
Frequency: 4.1-4.2GHz
Phase noise: -90dBc/Hz at 1KHz offset.
tuning: voltage tunability in the frequency range.
temp range:-30 to +60deg C
Now,DRs come with different properties,eg.
High Q, High dielectric constant >30,different shapes(disk,cylindrical etc.),linear
with frequency.
How to go about this and select a DR for designing a DRO?
I
The VCOs come with wide tuning range,but quite bad close-in phase noise.
My application demands,best possible phase noise,atleast an improvement of 10 folds over
VCO based PLL.
I looked for options, and found that DRO based carrier generation has potential to do so.
Being very new to this area,I wish to take help of forum members,while selecting an appropriate
dielectric resonator for designing a DRO to generate frequencies close to 4GHz.
My design specs are something like this:
Frequency: 4.1-4.2GHz
Phase noise: -90dBc/Hz at 1KHz offset.
tuning: voltage tunability in the frequency range.
temp range:-30 to +60deg C
Now,DRs come with different properties,eg.
High Q, High dielectric constant >30,different shapes(disk,cylindrical etc.),linear
with frequency.
How to go about this and select a DR for designing a DRO?
I
some available literature says, DRs can be tuned mechanically 0.2 to 3% of the resonant frequency.
I found that people have used DRs with εr=30 and Q=6000 for the band stated above.
But nobody explains ,the selection criteria.
Is it possible to lock DRO with integer-N or fractional-N PLL ? I found only sampling phase detectors
being used for phase locking DRO, any particular reason for this?
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