Bias point for class AB power amplifier CMOS in Cadence
时间：04-04
整理：3721RD
点击：
Hello!
I am designing in Cadence a power amplifier Class AB with output power 20dBm.
Supply voltage is 3.3V, frequency 2.4Ghz, cascode topology, 130nm CMOS .
What is the correct methodology for calculate the DC Bias for class AB amplifier?
I am designing in Cadence a power amplifier Class AB with output power 20dBm.
Supply voltage is 3.3V, frequency 2.4Ghz, cascode topology, 130nm CMOS .
What is the correct methodology for calculate the DC Bias for class AB amplifier?