[moved] HELP Testbench VGA CORE for AGC 10gbps

Hello everybody!
This is my first post, I have 2 years in microelectronics RFIC area. I am trying to design an AGC for optical receiver 10Gbps. I read a lot of papers and I know the blocks necessary to build it now I am in the VGA block but my principal problem is the testbench in cadence.

I am trying to measure S21 of VGA, but the result of simulation is very bizarre so I am sure that my problem is in the testbench.

I used this circuit before like FT doubler(Vin+ Vbias Vin-) and it works perfect, now to convert this into VGA I read that the difference is in the connections of the input Vin+ Vin- Vin+, but I have S21 like -300dB.

Please I want to know what I am doing wrong. Thanks a lot!.

Best Regards!

The balun is single ended=50, differential output=100