Design of Low Noise Amplifier in cadence (HBT)
I am a new one in RF IC design and I am trying to design my first cascode LNA at 30Ghz with cadence.
What I did already is finding my current density Jopt of my bipolar transistor and cut off frequency ft using these tbs https://community.cadence.com/cadenc...-transistor-ft and https://community.cadence.com/cadenc...os-transistors. What are the next steps that I should take into cadence for a good design? Maybe I have to change the sizing of the transistor and put inductive degeneration but I am not sure about the process in cadence od do the biasing next?
Could someone suggest me the steps that I have to take ? I cannot find a good analytical tutorial for beginners on this topic for cadence..
Thanks for all of your help!
You found the Optimum. OP for max. fT but it doesn't mean that you'll also find the Optimum Noise Figure.They are absolutely different things.
For an LNA with "lowest" possible NF, you should carefully either measure the NFmin by using Source-Pull technique or you may trust the model ( but the models are very poor in terms of Noise Figure ) and you have to find NFmin for a particular OP and frequency.Then you will find a Zopt that gives an impedance so that when the active device has been presented by this impedance at its input, you'll get lowest possible Noise Figure.
But I assure you that you have a long way to run.Getting available lowest Noise Figure is not easy at 30GHz.
If you don't have sufficient experience, I suggest you to read and work hard.