SYNC and CLK Generator
I want to generate LRCLK and BCLK signals for testing in one of my project. Requirement is they should be in sync of each other i.e., falling edge of both clocks should be same.
I can use dual IC 555 (LM556) and generate these two clocks in astable mode, but will they be in sync?
Can anyone one suggest some other simple solution, which will not require any programming to be done?
Thanks,
cjrathi
Hi,
It seems to be an I2S audio interface...
Please start with the specification. You may agree that 0.00% deviation is impossible. There must be any tolerance. This is what you need to take care of.
Then you need to say the ratio: BCLK_frequency/LRCK_frequency
A counter - clocked with BCLK -
and a compare wit a fixed value ( BCLK_frequency/LRCK_frequency -1)
causing a counter reset
.. may do the job.
There will be a small delay between BCLK and LRCK
If you want it even smaller, then use a DFF (D = counter_reset, CLK = BCLK, Q = LRCK). This reduces the the delay by (counter_delay + compare_delay).
If you want it even smaller, then you need have a clock source with 2 x BCLK. Then use two DFF to syncronize BCLK and LRCK.
Usually one uses a CPLD for this. But for sure you may use discrete logic as well.
***
Maybe you can (mis-)use an I2S transmitter to generate these signals.
Klaus
depends what you mean by "in synch". Like in synch to a femtosecond, or just repeatably in sych so the rising edges are within say 20 nanoseconds of each other.
The synch pulse you show can be generated by a divide by two circuit (flip flop) counting the clock, and you can enable a single pulse to output on the counter chip or possibly by adding a fast AND gate at the output of the counter. You could add some some capacitive delay to the clock output, to get the clock and synch pulse to match right up.
in other words, use one 555 chip, and one flipflop, and some sort of gate to only output ONE synch pulse when it is wanted.