How to reduce Harmonic Balance simulation time in Spectre

Hi, I am running Harmonic balance simulation for my circuit at different frequencies to find loadpull values but it takes lot of time sometimes even half a day to finish with all the frequencies. Especially it is slow at low frequencies in my case , for example at 4 GHz or 8 GHz. Is it usual to take this long? or what parameters I should consider changing in my circuit like biasing,Circuit stability, voltage source values, and transistor width and sizes?. I chose Number of Harmonics =11, Oversample Factor =9 and in loadpull section, I chose 40 number of steps for rho and phi. Thanks

Minimizing the number of distinct nodes and devices is key.

At my last employer they struggled with this too, and got a
lot of improvement by having one of the CAD group folks write
a Perl script that would combine parallel FET fingers into a
single m=XXXX device (rather than XXXX of them, which is
what comes from a M0<1023:0> type instantiation).

You might look to your schematic style and the netlist form,
to see whether you are dragging that kind of baggage. May
not be practical to do the same coding, but maybe you can
represent your circuit in a way that creates less solution
overhead. That is,

M0 NS NG NS NB w=xxx l=0.0yy nf=1024

instead of

M0<127:0> NS NG NS NB w=xxx l=0.0yy nf=8

or some such. In many technologies it's not practical
to make super high finger count FETs, tap rules force
you to break them up, and literal-minded designers will
represent the physical form N distinct active area
regions, hend N FETs) in the schematic even if a single
FET instance is just as realistic.

RF switches are one such critter. CMOS PAs, another.

Oversample Factor is too much that's why your simulation is so slow..
Since the waveform does not have extreme shape ( ringing,overshoot,hardly squared etc. ) you don't have to increase Oversample Factor much.
It should be 3-4 max. for sinusoidal-like waveforms.

Thanks. does M0<127:0> represent number of multipliers?. In my case I have 4 multipliers and number of fingers 125. But If I change it to just the number of fingers =125*4 and multiplifer =1, the output power that I get is decreased.

No.
This is a repeated instance.
However if you generate layout from schematic, this generates same layout as multiplier.

Surely consider physical device structure.
They give different layout.

Why do you set Oversample Factor =9 ?

Can you understand Harmonic Balance Analysis ?
Can you unsderstand a meaning of "Number of Harmonics" and "Oversample Factor" ?

Show me your netlist portion regarding analysis, option and save statment.

If such large "Oversample Factor" is truely required, use Shooting-Newton-PSS instead of HB-PSS.

Show me simulator logfile.

What are you simulating that requires an oversample factor of 9?
Here are some guidelines from Cadence website: https://community.cadence.com/cadenc...balance-part-1

I realized that it is because my circuit is unstable at the frequencies where I am doing loadpull.