Q3D modeling of a via array in a semiconducting substrate

I seek to model an array of copper vias embedded in a doped silicon wafer of conductivity 10^4 S/m in Q3D Extractor. With this level of conduction in the substrate what is the appropriate way to model this element? Should a source and sink be applied to the silicon and if so where? It would seem adding a source and sink to the top and bottom of the substrate would arbitrary force a conduction path vertically that may not truly exist.