Power consumption of continuous-time Delta-Sigma ADC vs. Incremental Delta-Sigma ADC
时间：03-29
整理：3721RD
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Hi all,
I have known that discrete-time(DT) DSM consumes more power than continuous-time(CT) DSM because of op-amp settling.
And CT Incremental ADC operate for a fixed number of clock cycle and then reset the modulator. So sample-by-sample conversion is achieved.
In general design, the GBW requirement for the op-amp under CT DSM is 2~3*fs. However, if we use the same op-amp to design CT Incremental ADC, SNDR will degrade.
So if we want the same SNDR, we need to increase the power in Incremental mode.
I have thought of several possibilities like the following:
1.For CT Incremental ADC, the op-amp need to reset after N clock cycle, so it requires large current during the reset cycle. Thus increasing the op-amp GBW requirement.
2.One paper shows that the signal to thermal noise ratio is different for both case. Operating a CT DSM in the incremental mode is therefore inherently noisy (worse by ~4).
Is there any other possible reason?
Another question is for the same OSR, coefficients, modulator order, input amplitude and quantizer bit, simulation shows that the SNDR for CT incremental ADC is higher than CT DSM.
For DSM, SNDR is related to OSR, modulator order and the quantizer bit.
For incremental ADC, SNDR is related to conversion cycle (N), coefficients, the max input amplitude and quantizer bit.
Are there more intuitive analysis above two case? Because the mathematical derivation of the two cases is not the same.
Thanks.
I have known that discrete-time(DT) DSM consumes more power than continuous-time(CT) DSM because of op-amp settling.
And CT Incremental ADC operate for a fixed number of clock cycle and then reset the modulator. So sample-by-sample conversion is achieved.
In general design, the GBW requirement for the op-amp under CT DSM is 2~3*fs. However, if we use the same op-amp to design CT Incremental ADC, SNDR will degrade.
So if we want the same SNDR, we need to increase the power in Incremental mode.
I have thought of several possibilities like the following:
1.For CT Incremental ADC, the op-amp need to reset after N clock cycle, so it requires large current during the reset cycle. Thus increasing the op-amp GBW requirement.
2.One paper shows that the signal to thermal noise ratio is different for both case. Operating a CT DSM in the incremental mode is therefore inherently noisy (worse by ~4).
Is there any other possible reason?
Another question is for the same OSR, coefficients, modulator order, input amplitude and quantizer bit, simulation shows that the SNDR for CT incremental ADC is higher than CT DSM.
For DSM, SNDR is related to OSR, modulator order and the quantizer bit.
For incremental ADC, SNDR is related to conversion cycle (N), coefficients, the max input amplitude and quantizer bit.
Are there more intuitive analysis above two case? Because the mathematical derivation of the two cases is not the same.
Thanks.
As your thread didn't get any answer since about 2 weeks time and will soon disappear from the first page of the Analog Design section (which is actually the correct section for your question), I've moved your thread to this Electromagnetic Design and Simulation section, perhaps you get an answer here - anyway it will stay longer at the first page.
There's still a reference to your thread at the Analog Design page.
One more chance could result from the publication of your question in one of the Designer's Guide community forums.
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