How to compare variables name
In particular one of those variable is the input of a task and the other one is a variable declared in the main.
module ex();
logic clk;
logic [ 3:0] btn;
logic vaux2_p;
logic vaux2_n;
logic gpio1;
logic gpio2;
main dut(
.clk(clk),
.btn (btn),
.vaux2_p (vaux2_p),
.vaux2_n (vaux2_n),
.pio3 (pio3),
.pio4 (pio4)
);
task test;
input [ 7:0] a;
input [23:0] v;
input [23:0] s;
integer f1;
integer f2;
begin
f1 = Sfopen("file.txt","w");
if (!f1) begin
Sdisplay("File \"file.txt\" cannot be opened!");
end else begin
if(s=="dut.f") begin
Sfwrite(f1, "1:\n");
end else if(s=="dut.f") begin
Sfwrite(f1, "2:\n");
end
end
endtask
initial begin
test(8'h1a,16'hF0, dut.f);
Sfinish;
end
endmodule
ASCII strings would be represented by string type, not bit vectors. There's however no direct access to object names. You may check if vpi_handle_by_name() serves your purposes.
Thanks for your reply, but it seems that vpi_handle_by_name() won't be useful in my case. Anyway I menage to compare the variables name in a different way. Thank you!
many years ago, some compilers/? would list all variables and what line they were on, in a program
it did not take into account subroutines and scope
perhaps your system has that capability
No I don't think my system has that capability, but using strings it has been possible to compare two variable names.
#2 I've noticed vpi handle in the vhdl standard? What is this?
Is this the way the software processes the rtl code.
Can you talk to modelsim/questasim or whatever software using these functions?
VPI is from verilog https://en.wikipedia.org/wiki/Verilo...ural_Interface though apparently it has been partially ported to VHDL as VHPI. I only saw a link for GHDL having support, don't know if any other simulators support it.
Mainstream Verilog/Systemverilog simulators support VPI and it's predecessor PLI, it's a way to access the database that the simulator creates directly with the C programming language.
