求大神帮助 关于DRC的 在线等
时间：10-02
整理：3721RD
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Protel Design System Design Rule Check
PCB File : Documents\PCB1.PCB
Date : 5-Aug-2014
Time : 08:22:34
Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the board )
Rule Violations :0
Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Prefered=0.254mm) (On the board )
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.254mm) (On the board ),(On the board )
Rule Violations :0
Processing Rule : Broken-Net Constraint ( (On the board ) )
Violation Net NetY1_2 is broken into 2 sub-nets. Routed To 50.00%
Subnet : C3-1
Subnet : 单片机-19 Y1-2
Rule Violations :1
Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0
Violations Detected : 1
Time Elapsed : 00:00:00
这些都是啥 是报错吗 大概怎么修改呢
PCB File : Documents\PCB1.PCB
Date : 5-Aug-2014
Time : 08:22:34
Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the board )
Rule Violations :0
Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Prefered=0.254mm) (On the board )
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.254mm) (On the board ),(On the board )
Rule Violations :0
Processing Rule : Broken-Net Constraint ( (On the board ) )
Violation Net NetY1_2 is broken into 2 sub-nets. Routed To 50.00%
Subnet : C3-1
Subnet : 单片机-19 Y1-2
Rule Violations :1
Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0
Violations Detected : 1
Time Elapsed : 00:00:00
这些都是啥 是报错吗 大概怎么修改呢
百度翻译已解决 谢谢