interconnects for nanometer design

For nanometer system-on chip SOCs design ,How should be the structure/ dimensions of the interconnects?...
is there any field simulation algorithm (such as FDTD) for analysing signal integrity in nanometer interconnects?..

hi venkat
just refer
1.C. Mead and L. Conway. Introduction to VLSI Systems. Addison-Wesley PublishingCompany, Inc., 1980.
2.A. Jantsch and H. Tenhunen, Networks on Chip. Kluwer Academic Publishers, 2003
3.D. Wingard, Tiles – An Architectural Abstraction for Platform-Based Design, EDA Vision, June 2002, available from www.edavision.com
4.h**p://ocpip.accounts2.kavi.com/pressroom/articles/namerica/2004/Interconnect-Centric_Design_Chap14_DWingard.pdf.
in this pdf file you will get some idea

Second book is available here:
https://www.edaboard.com/ftopic173614.html

Regards