请教：关于mos管的各种电容

在cadence里specter仿真的时候，print dc operating point 的时候，可以看到mos管的很多参数，最近有一个问题就是关于mos的寄生电容：Cgd,Cdg有什么区别和联系。类似的还有Cgs,Csg等等

Cxy和Cyx是cadence的算法问题,在Hspice里就没有,其实取Cxy就可以了,因为这两个的数值一般不会差太多,比如TSMC的工艺库,不过个别工艺库除外(原因不明,模型不好,或者工艺不行?),最好在Hspice里也仿真一下,就更保险了.

在BSIM3、4模型中，MOS中的电容是以某端点（x）的电压变化引起其它端点（y）的电荷变化来表示的（Cxy=Qy/Vx）。一般来说，各个电容都是非互易的，即Cxy不一定等于Cyx，因为很多电容并不能简单地等效为平板电容。比如，一定的电压变化量加在Gate端上所引起的Source端上的电荷变化量 与 Source端上相同的电压变化量所引起的Gate端上的电荷变化量并不相等。即Cgs不等于Csg。

蓝领工人讲的有道理

启发啊

不下了 英文的 看着费劲 哈哈

4.5 Extrinsic Capacitance: Overlap
Capacitance
An accurate model for the overlap capacitance is essential. This is especially true
for the drain side where the effect of the capacitance is amplified by the transistor
gain. In old capacitance models this capacitance is assumed to be bias
independent. However, experimental data show that the overlap capacitance
changes with gate to source and gate to drain biases. In a single drain structure or
the heavily doped S/D to gate overlap region in a LDD structure the bias
dependence is the result of depleting the surface of the source and drain regions.
Since the modulation is expected to be very small we can model this region with a
constant capacitance. However in LDD MOSFETs a substantial portion of the
LDD region can be depleted, both in the vertical and lateral directions. This can
lead to a large reduction of overlap capacitance. This LDDregion can be in
accumulation or depletion. We use a single equation for both regions by using such
smoothing parameters as Vgs,overlap and Vgd,overlap for the source and drain side,
respectively. Unlike the case with the intrinsic capacitance, the overlap
capacitances are reciprocal. In other words, Cgs,overlap = Csg,overlap and Cgd,overlap
= Cdg,overlap

摘自BSIM3V3 manual

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