求助——版图问题

我用assura 跑DRC结束的时候总会出现the specified run " 名字"in " 路径"is invalid.而且有些时候会出现failed to build VDB。cannot submit DRC run。
再问一个关于设计规则的问题，我现在用的是smic0.18的工艺库，有句规则不知道是什么意思。请知道的高手指点一下：latchup.guidance .3a:maximum spacefrom any point within source/drain region to the nearest pickup AA region inside the same well for I/O and internal circuits.
跑DRC提示上面的错误，不知道该怎么修改版图。

To overcome this problem you need to do a small change in the DRC rule file.First go to /RuleDecks/Assura/DRC, then open
"G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.10-p1.rul" file -> go to the last line which is "load( "./DRC/G-DF-LOGIC18-1.8V-3.3V-1P6M-Assura-drc-memory.rul" )".
Instead of "./" you give the full path of the file. For example
"load( "/cad/umc_180/RuleDecks/Assura/DRC/G-DF-LOGIC18-1.8V-3.3V-1P6M-Assura-drc-memory.rul" )". Hope this will work.

这位大侠你是在国外某论坛上看到的这些东西吧，我也看到了，只是看过以后还是不知道怎么处理。 3# icdreamer

试过了，果然搞定了。

2# icdreamer

latchup.guidance .3a:maximum spacefrom any point within source/drain region to the nearest pickup AA region inside the same well for I/O and internal circuits.
这个问题我也遇到了，是什么意思啊，怎么解决呢

我最近也遇到failed to build VDB。cannot submit DRC run。我解决方法是：在drc rule中include memory 将include相对路径改为绝对路径，OK

latchup.guidance .3a:maximum spacefrom any point within source/drain region to the nearest pickup AA region inside the same well for I/O and internal circuits.这个从别的帖子看到是仿制栓锁效应的一个规则。我出现这个问题是由于NMOS衬底接地，我省事没有画衬底，多打了衬底就好了。希望有用

遇到了这个问题，应该是衬底吧