VCO上电源的噪声
请问大家3个问题。
1、仿VCO时，如何在电源上加噪声，噪声文件怎么写?
2、芯片内部做一个LDO会不会比外加的电源噪声要小?
3、我们测试用得电源噪声有1mV.这对VCO的影响有多大，怎么仿真?
非常感谢大家的回复和帮助！
1. You can refer to Cadence document for noise format. As far as I remember, it is a two-column format. the first column is frequency and the second column is noise spectral density.
2. typically VCO will have its own regulator. The regulator reduces interference from other blocks that share the same power supply.
3. You can add a noise signal to your power supply (say, a sinusoidal), run transient sim and do FFT to check the Spur effect.
谢谢小编的回复，我已经在电源上加了LDO仿出来的噪声，相噪恶化了40dB.该怎样抑制电源上的噪声?需要重新做一个低噪声的LDO吗?
还想问大家一个问题，你们测试时用得电源是什么型号的?电源的噪声如何?谢谢大家的回复和帮助！
谢谢lakeoffire的回复，请问您noise spectral density的单位是什么?是V/sqrtHz, 还是v的平方/Hz.
还有关于噪声文件的格式是在cadence的那个文档里能找到?
非常感谢您的回复和帮助！
V/sqrt(Hz) is used in the noise profile. You can test it with a simple testbench that includes only a voltage source with the noise profile and run a noise simulation. I am not exactly sure which Cadence document describes the noise profile, but I guess you should be able to find that in User manual of Virtuso or similar documents. Good luck.
You can check the noise summary to find out which noise source dominates the phase noise and improve your design.
谢谢lakeoffire的回复和帮助！
Sorry I made a mistake in the noise file. I came across one of my testbenches today and found that the unit for noise should be V^2/Hz rather than V/sqrt(Hz). You can find that out also from Virtuso Cadence Circuit Simulator RF Analysis User Guide.
谢谢lakeoffire的帮助，噪声文件的问题已经解决，单位是V2/Hz。但是电源的噪声和VC控制线的噪声对VCO影响很大，因为VCO没有偏置电流，是低电压的。不知道该怎么解决。如何降低电源和VC对VCO的影响?希望得到大家的帮助！
普通的电源噪声不是很好，想要好的电源的话可以考虑直接用安捷伦某些测试仪器提供的低噪声电源（如5052）等
学习了~
学习中。
怎样测电压源的输出噪声?用什么仪器测量?谢谢大家的回复和帮助！
a spectrum analyzer should be able to measure the power supply noise.
Typically, VCO design requires a supply regulator to isolate the supply noise. For your VCO, you can characterize the gain Kvco and Kvdd, which is the vco gain referred to the Vctrl port and Vdd. There is tradeoff in Kvco selection. when it is large, the noise contribution is also large; when it is small, you lose tuning range. But at least a regulator could reduce the noise from Vdd, which contributes phase noise from Vdd directly to VCO output and also indirectly from Vdd to Vcntl and then to VCO output.
谢谢lakeoffire的回复和帮助！现在的问题是：我们老板要让我搞清楚是直接用电压源测试的相噪好?还是做一个LDO给VCO供电的相噪好?搞不清楚这个，老板不同意我做LDO。他认为电压源上输出的噪声低，而LDO本身也有噪声，不会改善VCO的噪声。
你好，请问你知道怎么在电路仿真中加噪声信号吗?analogLib里面的noise源是怎么用的?谢谢
同求。