ADC S/H amplifier 问题。 急求。

设计了个S/H(fiip-around) 的放大器 (gain=82db)，用理想的switch仿真SFDR，低频下SFDR有92db，但是高频200M输入下就变成了71db，按道理用的是理想的开关采样电路，SFDR不应该随输入频率发生这么大的变化，如果说我设计的运放有问题，那么低频下线性度不可能有92db，所以现在有些矛盾了，不知道问题出在哪里，求高人指点。

也可能是你的 OpAmp 設計造成的
Your OpAmp is supposed to settle to the required accuracy level before the end of each sample.
T_settle < 0.5 / F_sample
At low sampling freuquency, your OpAmp has long enough settling time.
At high frequency, your OpAmp may not have enough settling time.
To verify whether your OpAmp bandwidth / settling is the dominant factor, replace your OpAmp with an ideal OpAmp and conduct the S/H simulation again.

If you are talking about F_in (low frequency vs. 200 MHz), it would be similar issue.
Still OpAmp could be the dominant factor.

谢谢，我之前用过ideal amp 仿真，结果是好的，我设计的amp，bandwidth=1G，sample frequence=100M，slew rate什么的都没问题，Tsettle=1.5ns，而且运放只是工作在hold状态下，对于运放来说201M input signal is the same as 1M input.而且我试过将运放gain提高到140db，SFDR在200M input signal下就有93db。 但是这个还是无法解释gain=82db时候，低频输入下好，高频输入下不好。 还是存在矛盾。

不好意思， Tsettle是3ns。

May I know when you wrote
t_settle = 3 ns
To what accuracy level did you refer to?
For instance, (compared to steady state, i.e., the voltage level when t = infinity) the OpAmp settles to |V_infinity - V(3 ns after clock edge)| < 0.1%, ...
Assuming simple single-pole model,
Unity-gain bandwidth = 1 GHz
At F_in = 200 MHz, your OpAmp has open-loop gain about 5 only (in this order of magnitude).
You won't have good enough accuracy when you close the loop
-> your close-loop transfer function = (A_v(f)) / [1 + A_v(f)] (not close enough to 1).
Still bandwidth issue.

关注关注。

输入200MHz信号时，S/H的采样时钟是多少?
按照采样保持理论，频谱需要乘上Sinc 函数。
如果你的采样时钟频率与输入信号频率相差不大时，在频域上，Sinc会引起比较大的幅度下降
因此仿真时，可以适当增加S/H时钟看看，当然要满足运放的建立

能不能加QQ或者MSN详谈，忘指教。谢谢。我的QQ 313635795MSN: wk0728@hotmail.com

谢谢，采用时钟是100M。 输入是201.953125M

Sorry,我不用 MSN
我也沒有 QQ 帳號
我不知道
如果嚴重地不滿足
Nyquist sampling theorem 要如何 interpret FFT spectrum
我猜想
F_in 的 harmonic contents (2nd harmonic, 3rd, 4th, and so forth) will be folded back to in-band
但因 image frequency < 0 Hz, 再折 ...
有的 components 要再折好幾次
...
無言

还是非常感谢。哈哈

charge pass through?~