2-4译码器的Verilog - A代码求助

现在需要一个Verilog - A的译码器代码，两个数字输入和一个Enable信号s(s为零时，输出均为零)信号，四个输出。自己试着写了一个，当四个输入不变时，DC结果是正确的；但当输入为变化的时钟信号时，tran结果就不对了。即当in1 in0分别为00 01 10 11时，输出竟然out3=1,out2=out1=out0=0,且一直不变。还请各路大神不吝赐教！
代码如下：
module dec_2X4 (s, in1, in0, out3, out2, out1, out0);
output out3, out2, out1, out0;
input in1, in0, s;
electrical in1, in0, out3, out2, out1, out0, s;
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
parameter real tdel= 0 from [0:inf);
parameter real vtrans= 1.2;
parameter real vlogic_high = 1.8;
parameter real vlogic_low= 0;

integer a1;
integer a0;
integer y3;
integer y2;
integer y1;
integer y0;
analog begin
@ (initial_step) begin
V(out3) <+ 0;
V(out2) <+ 0;
V(out1) <+ 0;
V(out0) <+ 0;
a1 = V(in1) > vtrans;
a0 = V(in0) > vtrans;
end
if (V(s) >= vtrans) begin
y3 = a1 & a0;
y2 = a1 & ！a0;
y1 = ！a1 & a0;
y0 = ！a1 & ！a0;
end
else begin
y3 = 0;
y2 = 0;
y1 = 0;
y0 = 0;
end
V(out3) <+ transition( vlogic_high*y3, tdel, trise, tfall );
V(out2) <+ transition( vlogic_high*y2, tdel, trise, tfall );
V(out1) <+ transition( vlogic_high*y1, tdel, trise, tfall );
V(out0) <+ transition( vlogic_high*y0, tdel, trise, tfall );
end
endmodule

周董?

已经解决了。应该加上对四位输入变化的探测语句。