CMFB仿真时，如何搭建Testbench？

正在做全差分运放，需要仿真CMFB环路的稳定性，采用的stb仿真。我看到有人在仿真CMFB环路时，运放是开环的；而在我的理解中，应该根据实际负载来确定TestBench，由于运放一般闭环应用，因此是否应该将运放接成f=1等典型形式?
请大侠指教！谢谢！

顶顶！

帮顶一个

DDDDD

应该是开环仿真。加上实际工作时候的等效负载。

仿真共模反馈通路的开环

芯海科技没有说么 呵呵

应该是仿开环吧～～

9# zhongbo1127
芯海没说，呵呵

经过实际仿真，发现开环/闭环的幅频、相频曲线有显著不同，但是相位裕度基本一直。
在几个不同的共模反馈环路增益下进行测试，发现开环/闭环所得到的相位裕度偏差在3deg以内。
具体理论解释，暂不清楚。

you raised a good question:
shall we neglect differential mode feedback path (open loop or closed loop) during stability check of cmfb?
Answer is NO. You shall never assume differential mode feedback path doesn't have common mode gain.
The reason is quite simple:
at high frequency, CMRR drops significantly. so that differential mode path has common mode gain.
Choosing the right break point for cmdmprobe may help. But I suggest:
have your dm feedback in the cmfb test bench, but dm input can use a balun, such that it will get mqx common mode feedback through your dm path.
and then run you stb analysis.
Another way to verify cmfb is well designed, you can try to apply 'absolute stability' concept from microwave amplifier - i.e. make sure with all passive cm termination, the part is always stable.

感谢smzg大侠的精彩回复，谢谢！

学习了，高手总是隐身的么?