请教DAC SFDR仿真方法
oversampling要做, 因為你想看的是continuous的analog signal
请问在一个信号周期内的采样点数应该是等于Fsample/Fout，还是采样点数越大SFDR越正确
目前没有
我也不知道诶，学习。
学习学习，我也不知
采样点数就等于Fsam/Fout
一个信号周期内的采样点数就是等于Fsample/Fout
lz想问的应该是：是不是仿真的点数越多，SFDR就越正确
这个说法不完全正确 在仿真的点数小于一个信号周期的采样点数 仿的越多 SFDR越正确
如果在仿真的点数大于一个信号周期的采样点数 仿的越多 SFDR也还是和仿真的点数等于一个信号周期的采样点数的时候一样
因为信息量是一样的
请问采样点数一般采多少点?怎么确定?还有那个Fsample要怎么确定?
SFDR simulation for ADC or DAC is a little bit different. Correctly predict SFDR forDAC must follow
(1) Proper # of Pts in FFT and your simulation, basically, you need odd number of cycle of signal and have to keep 2^N ppt FFT. E.g. 10bit DAC, best case is to use 1024 pt. Depending on simulation time, most of case 256 ptcan also give us good SDFR prediction.
I don't agree above author said that increasing # of cycle have no use. This is because your cycle repeating. If cohence sampling cycle, definitely helps.
(2) Pls take out the unsettling or overshoot point during the transient simulation. That is to say, you must use true settling points for FFT. Otherwise your SDFR is harm.
Hopefully it helps
prof3 发表于 2009-3-19 15:26
SFDR simulation for ADC or DAC is a little bit different. Correctly predict SFDR forDAC must follow！ {& O( }+ T- g, R" j) u
(1) Proper # of Pts in FFT and your simulation, basically, you need odd number of cycle of signal and have to keep 2^N ppt FFT. E.g. 10bit DAC, best case is to use 1024 pt. Depending on simulation time, most of case 256 ptcan also give us good SDFR prediction.7 g: k) k5 x9 f; Ir( G' ]
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I don't agree above author said that increasing # of cycle have no use. This is because your cycle repeating. If cohence sampling cycle, definitely helps.
(2) Pls take out the unsettling or overshoot point during the transient simulation. That is to say, you must use true settling points for FFT. Otherwise your SDFR is harm.+ z, G, t3 @6 t
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在用matlab做分析时可以将unsettling or overshoot point取出来，但是实际用仪器测试时能否去除掉呢，毕竟输出是连续变化的，整个输出做fft分析
支持小编
支持小编
very agree with pros says
学习。
当不了沙泼还是要支持的！感谢感谢~
xue xi le
sample point=2^n
study
找不到原文，想学习一下
谢谢小编的分享了！
如果是16bit,那意思相当于说采样点数要达到65536个点?
DAC输出波形有建立和过冲，如果每个时钟周期取一个点，这些过冲就无法表现在频谱里了，个人觉得取点越多越好！
完全同意，应该不能把这些overshoot和unsettling的信息去掉
测DAC的SFDR一定要用matlab吗?可以用别的方法吗?比如说cadence里是否能看DAC的SFDR和SNR，如果能怎么看?我设计的是8bit current streeing DAC
I WOULD LIKE TO KNOW ABOUT SFDR