为嘛电路图和版图的PD AD PS AS等等不一样，也能通过LVS？

AS AD PS PD are the parameters for the parasitics.
When schematics are captured, these parameters (i.e., AD, AS, PD & PS) are not given.
It is OK (allowed) the netlist for LVS does not contain these parameters.
Under such circumstances, the physical layout verification tool only check if the primary parameters match (between database from netlist and database converted from layout).
Parasitic information is only extracted during the parasitic extraction flow.

谢谢回答啊！
我还想问一下，要是这些参数不一样，仿真结果会有差别吗?我觉得应该没有差别吧，关键参数不是这些，不知道您是怎么看的?

For high-frequency / high-speed circuits, the parasitics make simulation results a lot different.
For the simulation of ESD and I/O cells, since the drain-side layout is subject to ESD design rule, the parasitcs make a lot differences, too.
Without the correct AS, AD, PS, PD, the calculation of diode capacitance are much smaller.
For HV ESD cells, the drain-side RS and RD significantly increase the total RDS(ON).

请问一下，AD AS　PD PS 各自代表什么寄生参数? 谢谢！

care the match

S端D端的面积和周长

谢谢！

AD: Area of Drain
AS: Area of Source
PD: Perimeter of Drain
PS: Perimeter of Source
(
NRD: Number of squares of Drain
NRS: Number of squares of Source, ... and a lot more. ...)