关于verilogA求助

小弟要用verilogA写一个8位循环计数器
功能为：时钟上升沿触发，输入高电平输出加1，输入低电平输出减1
这是我写的程序：
`include "constants.h"
`include "disciplines.h"
module int_8b( B7, B6, B5, B4, B3, B2, B1, B0, Din, CLK);
electricalB7, B6, B5, B4, B3, B2, B1, B0, Din, CLK;
parameter real trise = 0.1u;
parameter real tfall = 0.1u;
parameter real tdely = 0.1u;
parameter real vlogic_high = 1.8;
parameter real vlogic_low= 0;
parameter real vtrans_clk= 0.9;
`define num_bits8
integer i;
integer m;
integer halfscal;
real fun[0:`num_bits-1];
analog begin
@ (initial_step) begin
i=0;
end

@ (cross(V(CLK) - vtrans_clk, +1)) begin
halfscal = 128;
if (V(Din) >= 0.9) begin
if (i=255) begin
i=0;
end
else begin
i=i+1;
end
end
else if (V(Din) < 0.9) begin
if (i=0) begin
i=255;
end
else begin
i=i-1;
end
end

for (m=(`num_bits-1); m >=0; m=m-1) begin
if (i > halfscal-1) begin
fun[m]=vlogic_high;
i = i - halfscal - 1;
end
else begin
fun[m]=vlogic_low;
end
halfscal = halfscal / 2;
end

end

V(B7) <+ transition( fun[7], tdely, trise, tfall );
V(B6) <+ transition( fun[6], tdely, trise, tfall );
V(B5) <+ transition( fun[5], tdely, trise, tfall );
V(B4) <+ transition( fun[4], tdely, trise, tfall );
V(B3) <+ transition( fun[3], tdely, trise, tfall );
V(B2) <+ transition( fun[2], tdely, trise, tfall );
V(B1) <+ transition( fun[1], tdely, trise, tfall );
V(B0) <+ transition( fun[0], tdely, trise, tfall );

`undef num_bits
end

endmodule
但是仿真时八个输出一直是0找了半天也没找到错误
大家帮我看看啊
跪谢啊！

发现一个
判断条件 ==

学习一下....