问 Verilog arms 是用来干什么的,和VerilogA区别?
时间:10-02
整理:3721RD
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Veriloga 用来做系统级建模
Verilog arms是用来干什么的呢?
Verilog arms是用来干什么的呢?
mixed signal
I guess it is typographical error.
Verilog-AMS.
Refer to the URL for more information:
http://en.wikipedia.org/wiki/Verilog-AMS