一个关于PLL的问题？

a large amount of power consumption cannot be avoided in high frequency operations because internal nodes of the con-PFD are

not completely pull up or pull down.

我在好多文章都看到过这句话！一直补能理解。高手指点一下

功耗大不是因为电流太造成的吗?和the con-PFD arenot completely pull up or pull down有关系吗?

What does "con_" in "con_PFD" mean?

If internal nodes are not completely pull up or down, the DC current will appear. For example, if input to inverter is HiZ, big current will appear in that inverter.

con_PFD 是conventional PFD
直流电流作为偏置电流不是一直存在的吗? 能详细解释一下 为什么con_PFD are not completely pull up or pull down时，直流电流出现吗?“HiZ”什么意思?谢谢

同文
pull uppull down好像是个好难缠的问题啊，有没有大侠解释一下? 谢了

不太清楚lz讲的话, HiZ, 是high impedance的意思. 如果一个digital circuit cannot be completely pulled down/up, then both the pull-up network and pull-down network will be turned on, or at least partially turned on. This gives a direct between the two power supply rails. Therefore, it gives a high power consumption.

Exactly！

The conventional low speed (less than 2.5Gbps) PFD should be constructed with static logic gates. Thus, it will suffer from big current issue mentioned above.

If PFD is constructed with high speed gates (refer to 10Gbps circuits), constant bias current will be there.

Thanks all

HiZ HiZ