求教 PLL 问题

如果相位误差是0，说明输出频率是osc的自由振荡频率，当你想要的信号和这个频率不同的时候，你就得在vco输入端加一个非零控制电压，就是相位误差。

请问您能具体解释一下为什么会存在一个固定的相位误差吗?谢谢！

is your PLL CPPLL?

refer to Razavi's book

the static phase err come from noidea effect,
first, you need to check your PFD, make sure no timing err between UP/UPB, dn/dnb
second, make sure your charge pump is working, no charge/discharge current, no clock feedthough effect,
third, make sure your loop filter no leakage current,
4th, make sure you VCOis work absolutely synmertic.
5th, make sure your divider no timing err.
if all no-idea effect is in your brain, the static phase err will be very low, I think which less than 50ps.

电荷泵有问题；电流失配，电荷注入。仔细查查

固有频差

先看看reference Spur有多大，然后再看。也许pll根本就不存在什么相位差，是你的测试方法或者测试的途径引入的