有个DC-DC仿真的问题请教大家
时间:10-02
整理:3721RD
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我用下面的图来做仿真:电路图见附件,下载附件不会扣积分的,请放心。
我用的是Hspice,代码是DC-DC boost
*Set options
.option post probe
*Element Statements
Vg Vg 0 3
LVg Vx 100.0u
* COMMENTS YOU CAN CHOOSE DIFFERENT TYPE FOR DIODE
D1 Vx vo DPPNWJU area=1
*DIODE
*D1 Vx Vo DPPNW area=1
R1 Vx Vo 1k
CVo 047.0u
RVo 0.1k
M1 Vx Ctr 0 0 cmosn w=100u l=1.2u
*R2 Vx 0 10k
Vpctr Ctr 0 pulse(0 3 0.1u 0.1u 0.1u 2.6u 5.0u)
*Control statements
*DC Vg 1.2 3 0.1
.tran 200p 20.0u
.probe V(Vx) V(Ctr)
.op
.include "./35um_model.sp'
.lib './diode.lib' diode_typ
.include cmos06.mod
.end
仿真出来时Vo=Vin,怎么没有升压啊,是什么原因啊?请大家不惜赐教
我用的是Hspice,代码是DC-DC boost
*Set options
.option post probe
*Element Statements
Vg Vg 0 3
LVg Vx 100.0u
* COMMENTS YOU CAN CHOOSE DIFFERENT TYPE FOR DIODE
D1 Vx vo DPPNWJU area=1
*DIODE
*D1 Vx Vo DPPNW area=1
R1 Vx Vo 1k
CVo 047.0u
RVo 0.1k
M1 Vx Ctr 0 0 cmosn w=100u l=1.2u
*R2 Vx 0 10k
Vpctr Ctr 0 pulse(0 3 0.1u 0.1u 0.1u 2.6u 5.0u)
*Control statements
*DC Vg 1.2 3 0.1
.tran 200p 20.0u
.probe V(Vx) V(Ctr)
.op
.include "./35um_model.sp'
.lib './diode.lib' diode_typ
.include cmos06.mod
.end
仿真出来时Vo=Vin,怎么没有升压啊,是什么原因啊?请大家不惜赐教
电路图