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音频放大器:
Class AB amplifier efficiency in SE configuration
Q: A customer wants to use a TPA711 in SE mode to drive a 15 Ohm speaker. Could you provide some design equations for calculating the efficiency of the audio amp and also the average current drawn so that i can calculate the amplifier dissipation. There is a detailed calculation for BTL in the datasheets.
A: The equations for efficiency for BTL and SE are the same except for the IDDrms calculation. For SE, IDDrms = Vp/(pi*RL) or half the value for BTL. This will make the amplifier twice as efficient as BTL for the same output power. Keep in mind these equations are only valid for sine waves and they assume the user has gotten rid of the DC current that will be flowing in single ended configuration. This can be done by using a DC blocking cap or tying the other end of the speaker to Vdd/2 instead of ground.
If this DC current is not removed, then an additional power dissipation of Vdd^2/RL will be occur, which will cause a drop in the efficiency of the system.
TAS5630 ambient temp
Q: I would like to use the TAS5630 for an industrial application. What will happe if i use it in an environment with an ambiante tempeature higher than 70°C (Reduce the MTBF, malfunction, reduce the performance?). Is it expected in the future an industrial range for this type of component?
A: Officially, the manufacturer (TI) does not guarantee ANY device specs or even device operation outside of the noted operating temperature range.However, many consumer devices will operate just fine under typical 'industrial' ambient operating conditions. Specs that typically change at high temperatures include increased noise and worse power vs. thd performance. Also, the device may go into thermal protection when outputting "normal" power levels. For abnormal operating conditions it is best to test the specs that are important to your system at the extreme conditions.
One point that is hard to test, but is a very legitimate concern is long term device operation. If a device is consistently operated outside of the specified conditions, long term reliability may suffer (i.e. the device may fail well before the expected lifetime is up). Again, this goes back to the point that the manufacturer does not guarantee operation outside of the specified range.
Does TPA3124 support 3ohm load?
Q: Is there any performance data of the TPA3124 for the following condition: Output power=stereo 5W, load=3ohm, PVCC=12V, SE mode.
A: Here is the performance for 3 ohm load at 12V PVDD.
2350.TPA3124 Output Power THD.pdf
Note: 3 ohm load is only supported in single ended mode.
General Suggestions on TDMA Noise in portable products
TDMA noise is a problem in many portable and office audio products. This discussion is taken from a correspondence with a customer, and it contains a few general recommendations on how to improve TDMA noise in a general audio application. This particular application is for a subsystem - an amplifier with both headphone (HP) and speaker (class-D) outputs integrated into a single package. Please feel free to add comments or suggested troubleshooting methods to this discussion post.
The first step in TDMA noise troubleshooting is figuring out how the noise is getting into the system. There are three common injection/coupling paths to check regarding TDMA noise:
Inputs
The TDMA noise could be coupling into the system along the input traces leading to the amplifier device. To check this, try disconnecting the amplifier's input capacitors from the PCB and AC GND the inputs of thedevice (AC GND the input pins as close to the device as possible). If the TDMA noise goes away, then the noise is likely coupling onto the inputs and transmitting through the amplifier.
In this case, ensure that the input traces are buried under a GND plane. Also, ensure that the shielding for the audio portion of the product is independent of the antenna and RF portions of the phone (or receiver). Finally, make sure that the input traces are not crossing or overlapping with any other board level traces that could carry the TDMA noise – particularly supply traces or RF traces.
Headphone only OR class D only
If the TDMA noise is heard on the HP only or the class D only, it is likely that the inputs to the amplifier are not to blame. In this case the noise could be getting into the system by either directly coupling onto the output traces, or by coupling onto a power supply line that only connects to the HP or class D of the amplifier.
In this case, ensure that the output traces of the affected output are buried under a GND plane if possible, and that they are not exposed to any RF traces. Also, see if the noise can be improved by increasing the value of decoupling capacitors for the supply lines to the affected output (such as HPVDD, or VBatt – assuming these are supplied via separate references).
Regarding the decoupling capacitors, please ensure that all decoupling caps are connected to the top GND layer. Sometimes capacitors are grounded to an inner layer using vias. This is not recommended as it can increase the AC impedance between supply and ground, which can make TDMA noise issues worse.
Headphone AND class D (but not input traces)
If the TDMA noise is present on both the HP and class D amp, but does not seem to be injected through the input traces, check the supply references that are used by both systems (primarily, check Vbatt. Try improving the decoupling on this line by increasing the value of the decoupling cap, and ensure that it is well grounded in the system). If this third situation is the case, the signal could also be coupling onto both sets of output traces, or onto the inputs after the input capacitors (not likely – but possible). Try shielding these areas from the antenna and see if the noise goes away.
Lastly, related to all of these points, check how the amplifier's GND balls are connected to the system. The best performance TDMA noise performance is usually achieved by connecting the GND ball(s) to both the inner GND layers and to the top GND layer. This provides the lowest impedance AC path from the supply lines to system GND, and should improve TDMA noise in almost all cases.
I2C supply voltage, DVDD of TPA2051D3
Q: Could the DVDD and the I2C supply voltage be different for TPA2051?
A: DVDD and I2C supply voltages can be different, but there are some conditions:
1) DVDD must be less than or equal to the system SDA/SCL VIH. In other words, the second case you stated does not work.
2) The I2C supply voltage must be less than the Abs max rating for SDA and SCL (3.6V for TPA2051) and less than PVDD. So if PVDD =3V, I2C Supply must be less than 3V.
Please see page 20 of the TPA2051D3 datasheet for more information.
Measuring the impedance of a loudspeaker
Surfing thru the forum, you'll see many threads related to short-circuit protection and over-current protection problems. These are usually caused by one of two things: 1) a poor output filter design, or 2) an unknown dip in speaker impedance.
For #2, if you use a DMM to measure the speaker impedance, you only get part of the picture - DC. Since a speaker is comprised of a complex impedance, you really need to measure it across frequency.
You might find this article very helpful then:
http://ap.com/kb/show/12 this is the knowledge base article that explains how to measure complex impedances using the AP. You may have to register (free account) on the AP sight, but worth it as they have quite a few articles there.
There is a really good overview (actually, almost covers the whole thing) written from the perspective of measuring a loudspeaker here: http://www.ap.com/kb/show/187#sound just scroll halfway down the page until you get to the “Sound Advice” heading.
The threshold of gating temperature for SPK_EN bit of TPA2018
Q: Our customer would like to know the threshold of gating temperature for SPK_EN bit of TPA2018. We could not find it in datasheet. Is it 150 degreeC? Could you please help to provide it? Thank you.
Also, the customer has been running devices continuously for 3-5 days. Some devices are shutting down, and are not restarting after a SW shutdown and reset. Some of these devices are indicating a thermal shutdown, some are not. Customer is not checking the Fault register (indicates over current shutdown) on the devices that did not show thermal shutdown. All devices restarted after a HW reset. What could cause this?
A: The typical thermal shutdown of the device is 170C, with a hysteresis of 20C. This means the device will shutdown when the built-in temperature sensor reaches 170C, and the shutdown bit will clear when the sensor cools to 150C.
Regarding the second question:
Both the Thermal shutdown bit (register 0x01, bit D2) and the Fault/Over current bit (register 0x01, bit D3) indicate a fault by reporting a '1'. In order to clear these registers, a '0' must be written to the register. If a software shutdown and restart is performed, these registers will preserve the previously reported information. The device will not be able to enter Play mode until these bits are cleared. Performing a hardware shutdown and restart will reset these bits to '0' which would allow the device to begin playing again.
Please ensure that the customer is writing '0' to the Thermal and Fault bits to clear them, or make sure the customer is performing a HW restart.
PCM1801 Serial Data format
Problem:
In the data sheet the serial data format is not given in relation to input voltages. It appears that a signal on the Vin pin is internally referenced to 2.1V. An analog signal passed throught the recommended external 1uF cap would then swing above and below with a maximum of 2.828 Vpp as given in the data sheet. Does this then mean that a maximum digital value would be obtained with an an analog input signal of no more than 2.828Vpp.
Solution:
The internal Vmid is 2.1 Volts. If the signal is ac coupled, that means that the signal can swing 2.8 Volts peak to peak or +/- 1.4 Volts around a midpoint of 2.1 Volts which is OK. The output code of the ADC is 2's compliment; therefore, a voltage below midpoint would be represented with the MSB set to a logic one. If the input exceeds 2.8 Volts, a constant value of positive full scale will be output.
PLIMIT Calcluation for TPA3112D1
Q: The customer needs some help calculating the voltage divider for the PLIMIT of the TPA3112D1. Here are his system requirements:
PVCC = 24V, Rl = 8Ohm, Rs = 310Ohm, Gain = 26dB and Power = 15W.
A: A good approximation for calculating Plimit is that your unclipped (THD <1%) peak voltage will be PLimit*4.5*.75
The reason for the .75 is that as your output reaches Plimit*4.5, the waveform will start to clip (as it does when it approaches a normal power rail).
If the customer wants unclipped output at 15W, they should apply 4V on the PLimit pin.
If the customer wants clipped output at 15W (more speaker protection), 3.45 should be applied to PLimit.
Quick Reference guide to Max output power of a Class D amplifier
Q: Can you comment on a Class D's max output power for a given power supply and load?
A: The pdf file attached at the end of this post shows how to approximate the max output power for a Class D at a given PVDD and load. It uses the TAS5613 as an example with PVDD = 24V and a 4 ohm load.
What the file shows is that the RDSON of the device creates a voltage divider with the load. It shows that the largest unclipped sine wave will have about 65W and a clipped signal (10% THD) will be 81.6. Note that the calculation of 10% THD is an approximation that says P_clipped = 1.25* P_unclipped.
If RdsOn were 0 ohm resistance (ideal output stage), the power would be 72W unclipped and 90W clipped.
Shutdown mode consumption of TPA2051D3
Q: For the TPA2051D3 the datasheet lists a supply current 1uA Max in full shutdown mode. Is it HW shutdown or SW shutdown?
A: BOTH!!!!!! For HW shutdown the typical value is 0.2uA with a max of 1uA; For SW shutdown the typical value is 0.2uA with a max of 1uA
数字音频接口
TPA5051 Audio Pops when switching delay
Q: Just looking for confirmation that when you want to change the delay, you need to soft mute the audio before the delay change to avoid a pop. My application is to use a gui to adjust the delay in my system. I have a slide bar and the I can slide the delay from max to min.
A: There should not be any pop when changing the delay on the fly. The device will mute itself until the RAM is filled beyond the set delay time. The I2S bus is simply 0 during this time. Pop/Click is caused by DC ramping too fast or too slowly at the output. The output caps will have already charged by this point.
TPA505XEVM GUI get stuck
Q: When running the GUI, the I2C status light turn red most of the time. Need to reset the board, unplug and plug in the USB,
and run the GUI, the I2C status turn Green.
However, touching any of the buttons or changing any registers, the GUI simply get stuck, the reoccurrence is 100%.
Have try numerous times, also with PC reset, same problem occurs.
The GUI is downloaded from the product folder which is version 2.0
A: It works after removing the J3-J5 corresponding to address 0.
A: Alternately, you could change the I2C address in the GUI.
音频转换器
[AIC3254] How and when can the C-RAM and I-RAM of the miniDSP be accessed?
I. When a miniDSP is powered off:
Its C-RAM (or coefficient memory) can be accessed by the control bus. The miniDSP does not have access to C-RAM.
Its I-RAM (or instruction memory) can be accessed by the control bus. The miniDSP does not have access to I-RAM.
II. When a miniDSP is powered up (non-adaptive mode):
Its C-RAM can be accessed by the miniDSP. The control bus does not have access to C-RAM (reading the registers return 0x00).
Its I-RAM can be accessed by the miniDSP. The control bus does not have access to I-RAM (reading the registers return 0x00).
III. When a miniDSP is powered up (adaptive mode):
One of the C-RAM buffers can be accessed by the miniDSP. The control bus has access to the other C-RAM buffer.
Its I-RAM can be accessed by the miniDSP. The control bus does not have access to I-RAM (reading the registers return 0x00).
Applying a software or hardware /RESET clears C-RAM to default and resets all other registers. I-RAM remains as programmed until power is removed.
Having said the above, C-RAM is shared with both miniDSP and PRB modes. I-RAM is unrelated to the PRB modes and only applies to miniDSP mode. The user can program I-RAM beforehand, use PRB mode and then switch to miniDSP mode. However, the DACs and ADCs must be powered off before switching.
Additionally, C-RAM should be programmed each time with the correct data according to each mode (PRB or miniDSP). A software reset will set C-RAM coefficients automatically for PRB modes.
For more details on C-RAM access refer to: http://focus.ti.com/lit/an/slaa425b/slaa425b.pdf
[AIC3254] miniDSP_D_Cycles and miniDSP_A_Cycles
The miniDSP_D_Cycles and miniDSP_A_Cycles property in PuerPath Studio are the number of cycles allocated per word clock frame. The lower the number of cycles per frame, the lesser power consumption.
In PurePath Studio, the cycles are set according to the amount of processing required. If the code is compiled and there is an error showing that the resources are exceeded, increase the number of cycles. Likewise, if you set the cycles to 904 and you have little processing in the process flow, you can reduce the number of cycles to reduce power consumption.
In terms of the device register map, the cycles shown is PurePath is the same as the IDAC and IADC values. PurePath has a macro in the SystemSettingsCode property of the framework that automatically configures IDAC/IADC based on the miniDSP_D_Cycles/miniDSP_A_Cycles, respectively. Also, there is another macro that will set the interpolation and decimation factors depending on the framework. For example, the AIC3254_8x4x franework will configure Interp and Decim to 8 and 4, respectively.
Also, IDAC and IADC must be an integral multiple of the interpolation and decimation factors, respectively. PurePath does quantize IDAC/IADC automatically in the property window to accomodate this restriction.
In general, the main restriction in terms of configuration is that IDAC>=MDAC*DOSR and IADC>=MADC*AOSR.
Other than that, there are cases where sync mode is required for the miniDSP. At the moment of this writing, there are no components in the GDE that require this mode. Nevertheless, the restrictions are described in the design note below. As long as p0_r60_b7 is '0', then these restrictions do not apply.
http://e2e.ti.com/support/data_converters/audio_converters/w/design_notes/aic3254-what-is-the-purpose-of-p0-r60-b7-6.aspx
Also, below is some information on C-RAM and I-RAM access for reference:
http://e2e.ti.com/support/data_converters/audio_converters/w/design_notes/aic3254-how-and-when-can-the-c-ram-and-i-ram-of-the-minidsp-be-accessed.aspx
[AIC3254] What is the purpose of p0_r60_b7-6?
The idea of p0_r60_b7 is to be able to transfer data between both miniDSP_A and miniDSP_D by making sure that both are locked together.
Whenever p0_r60_b7 = 1:
- DAC_CLK value is automatically forced to be used instead of NADC divider output (ADC_CLK). This ensures that miniDSPs have the same clock source. This is similar behavior as if NADC divider is shut down when p0_r60_b7 = 0, but is performed automatically when p0_r60_b7 = 1.
- The user must program IADC = IDAC = MDAC*DOSR = MADC*AOSR.
- To power the miniDSPs
- Power up ADC channel first at p0_r81_b7-6 (ADC will remain powered down until DAC is powered).
- Power DAC at p0_r63_b7-6.
- Power-up NDAC divider.
- To power down miniDSPs (failure to follow correct order will keep miniDSP_A running).
- Ensure p1_r59_b7 = '0' and p1_r60_b7 = '0' and then power down ADCs at p0_r81_b7-6.
- Power down DACs at p0_r63_b7-6.
- Power down NDAC divider
Whenever p0_r60_b6 = 1:
- miniDSP_D will be powered automatically when miniDSP_A is powered at p0_r81_b7-6. However, the DAC channel will be muted (e.g. nothing will play out of the interpolator output).
- If audio playback is desired, then the DAC must be powered up at p0_r63_b7-6.