EDA 程序改错

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SN74HC153 IS
  PORT(D0,D1,D2,D3:IN STD_LOGIC;
        A1,A0:IN STD_LOGIC;
        Y:OUT STD_LOGIC);
END SN74HC153;
ARCHITECTURE rtl OF SN74HC153 IS
SIGNAL temp:STD_LOGIC;
  BEGIN
   temp<=A1&A0;
   PROCESS(D3,D2,D1,D0,temp)
     BEGIN
      CASE  temp IS
        WHEN "00"=>y<=D0;
        WHEN "01"=>y<=D1;
        WHEN "10"=>y<=D2;
        WHEN "11"=>y<=D3;
      END CASE;
    END PROCESS;
END rtl;
哪里有错?语法方面的

temp为两位矢量，应为"std_logic_vector(1 downto 0)"

1.END SN74HC153;应该是：END ENTITY SN74C153;
2.PROCESS(D3,D2,D1,D0,temp)  应该要在后面加 IS
3.END rtl;   应该是END  ARCHITECTURE rtl;
4.A1,A0:IN STD_LOGIC;和SIGNAL temp:STD_LOGIC;应该都定义为STD_LOGIC_VECTOR(1 DOWNTO 0);