High-Speed, Analog-to-Digital Converter Basics

At first, aliasing may appear to be undesirable. However, it can be very useful. The most useful property is mixing a higher frequency signal to a lower frequency signal. For the system designer, this can translate into cost savings, power savings, or board-space savings by removing the need for an additional mixer in designer’s schematic. To achieve these desirable savings, care must be taken in the frequency planning and ADC selection. 这是从这篇文档中摘出来的一个问题，为什么可以用ADC来替代混频器，技术优势在哪里？成本优势在哪里？

One question that arises is, If the clock slope is of concern, then why not supply the ADC with a square wave clock? The answer is that square wave clocks also are a viable ADC clock option. The designer must be aware of a couple of trade-offs, however, when considering a sine wave or a square wave clock.
One trade-off is the creating of a low-jitter square wave clock versus the clock frequency range. In many applications, the ADC clock is run through a narrow band saw or crystal filter to improve the close-in phase noise (jitter) of the clock signal. After filtering, the clock is a low-jitter sine wave, which can be
applied directly to the ADC clock input. The trade-off of this approach is that the clock frequency range is now limited to the filter range. A few companies have invested in clock jitter cleaner or clock distribution chips. These devices offer improved phase noise performance, square wave outputs, and a wide range of clock frequencies. The phase noise of these devices may be sufficient to meet the required system performance without a clock filter.

这里选择正弦波，而不选择方波的原因似乎不止有这些，但是选择正弦波也有很大缺点，大家可以讨论一下，

这篇文章给大家看看

用ADC进行中频采样，对应的数学定理里面有下混频的功能，实际上并不需要这个混频器。

这个就是一个优势。相当于省了一级的混频器。

举个例子，用122.88Mh的信号采集第三奈奎斯特域的中频的信号，采集后信号会在第一奈奎斯特域出现。

也就是说省了一个数字下变频中的混频器，但是实际上这个混频器其实没有需求的，可不可以这样理解，