spyglass Run Design Read 报很多错误。大家一般是怎么解决

spyglass是如何编译厂商的库的?

STX_VH_202 (1) : Design units must be current with respect to their dependent units; otherwise require recompile.
The architecture 'RTL' in library 'WORK' is out-of-date because it has been compiled earlier than the entity 'RP301_RP2ETH_CRC' in library 'WORK'; Please recompile it.(entity(WORK.RP301_RP2ETH_CRC) TimeStamp(Wed Aug9 17:34:17 2017);architecture(WORK.RP301_RP2ETH.RTL) TimeStamp(Wed Aug9 17:34:17 2017))

STX_VH_202 (1) : Design units must be current with respect to their dependent units; otherwise require recompile.

The architecture 'RTL' in library 'WORK' is out-of-date because it has been compiled earlier than the entity 'RP301_RP2ETH_CRC' in library 'WORK'; Please recompile it.(entity(WORK.RP301_RP2ETH_CRC) TimeStamp(Wed Aug9 17:34:17 2017);architecture(WORK.RP301_RP2ETH.RTL) TimeStamp(Wed Aug9 17:34:17 2017))

自己顶一下，希望有人帮忙

求大神解答

給一下腳本 我來研究一下~

我是在刚开始是在GUI界面操作的,后来用的sg_shell。不知道怎么写一个自动化的脚本。希望得到您的帮助。还有就是cdc分析时sgdc文件的编写不会，不知道您有没有相关资料。我看了spyglass 的 user guid。感觉帮助不是很大。感谢您的帮助。谢谢您！

#Xilinx Library Files-- Common to all Xilinx designs

read_file -type verilog/applics/xilinx/xilinx_vivado_2016_3/Vivado/2016.3/data/verilog/src/glbl.v

set_option lib unisim/RRU_FPGA/jiansong/Project_Spyglass_hdl/BB_FPGA/unisim

set_option lib unimacro/RRU_FPGA/jiansong/Project_Spyglass_hdl/BB_FPGA/unimacro

set_option y/applics/xilinx/xilinx_vivado_2016_3/Vivado/2016.3/data/verilog/src/retarget

set_option y/applics/xilinx/xilinx_vivado_2016_3/Vivado/2016.3/data/verilog/src/xeclib

set_option y/applics/xilinx/xilinx_vivado_2016_3/Vivado/2016.3/data/verilog/src/unimacro

set_option libhdlfilesunisim/applics/xilinx/xilinx_vivado_2016_3/Vivado/2016.3/data/vhdl/src/unisims/unisim_retarget_VCOMP.vhd

set_option libhdlfiles unimacro/applics/xilinx/xilinx_vivado_2016_3/Vivado/2016.3/data/vhdl/src/unimacro/unimacro_VCOMP.vhd

# Source files –Design Specific

read_file -type sourcelist sources.f

#Set Top module

set_option top BB_FPGA_top

# Designread options

set_option enableSV yes

set_option language_mode mixed

set_option sort yes

#Run Design Read

link_design

#Run lint

current_goal lint/lint_rtl -topBB_FPGA_top

run goal

current_goal lint/lint_abstract-top BB_FPGA_top

run goal