sva断言log信息分析
时间:10-02
整理:3721RD
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各位,一个简单同步低有效复位D触发器
模块简略代码:
input a,rst,clk
output q
always @(posedge clk)begin
if(!rst)
q <= 1'b0;
else
q <= a;
end
sva_src.sv:
sequence s1;
rst;
endsequence
property p1;
@(posedge clk) s1 |->
(a, $display("P1 assert a = 1 is success\n"));
endproperty
a1: assert property(p1);
testbench.sv:
initial begin
clk = 1'b1;
rst = 1'b 0;
a = 1'b0;
#6 rst = 1'b1;
end
always #1 clk = ~clk;
always @(posedge clk)
a = ~a;
initial begin
#100 $stop;
end
执行以后打出如下log:
"sva_src.sv", 29: testbench.st.ss.a1:assert at 8ns failed at 8ns
Offending 'a'
P1 asserty a = 1 is success
"sva_src.sv", 29: testbench.st.ss.a1:assert at 12ns failed at 8ns
Offending 'a'
P1 asserty a = 1 is success
想问一下,从波形上看,以及打印的success信息,明明已经成功了的,红色字体的log信息中的failed的什么意思?
Best Regards!
模块简略代码:
input a,rst,clk
output q
always @(posedge clk)begin
if(!rst)
q <= 1'b0;
else
q <= a;
end
sva_src.sv:
sequence s1;
rst;
endsequence
property p1;
@(posedge clk) s1 |->
(a, $display("P1 assert a = 1 is success\n"));
endproperty
a1: assert property(p1);
testbench.sv:
initial begin
clk = 1'b1;
rst = 1'b 0;
a = 1'b0;
#6 rst = 1'b1;
end
always #1 clk = ~clk;
always @(posedge clk)
a = ~a;
initial begin
#100 $stop;
end
执行以后打出如下log:
"sva_src.sv", 29: testbench.st.ss.a1:assert at 8ns failed at 8ns
Offending 'a'
P1 asserty a = 1 is success
"sva_src.sv", 29: testbench.st.ss.a1:assert at 12ns failed at 8ns
Offending 'a'
P1 asserty a = 1 is success
想问一下,从波形上看,以及打印的success信息,明明已经成功了的,红色字体的log信息中的failed的什么意思?
Best Regards!
波形呢?