求助：在连接seq_item_port与seq_item_export时出错

各位：
目前正在学习UVM，在agent中将driver的seq_item_port与sequencer的seq_item_export连接起来的时候，nc报错TYCMPAT，大致是说类型不一致?可是port与export相连会类型不一致么，这个问题还是第一次碰到，有没有高手能帮忙解答一下?
相关代码如下：
axi_master_agent:

1. class axi_master_agent extends uvm_agent;
   
2. axi_configcfg;
   
3. axi_master_write_sequencerwrite_sequencer;
   
4. axi_master_write_driverwrite_driver;
   
5. 
   
6. `uvm_component_utils_begin(axi_master_agent)
   
7. `uvm_field_enum(uvm_active_passive_enum,is_active,UVM_DEFAULT)
   
8. `uvm_field_object(cfg,UVM_DEFAULT|UVM_REFERENCE)
   
9. `uvm_component_utils_end
   
10. 
    
11. function new (string name ,uvm_component parent);
    
12. super.new(name,parent);
    
13. endfunction : new
    
14. 
    
15. extern virtual function void build_phase(uvm_phase phase);
    
16. extern virtual function void connect_phase(uvm_phase phase);
    
17. extern virtual function void update_config(input axi_config cfg);
    
18. 
    
19. endclass : axi_master_agent
    
20. 
    
21. function void axi_master_agent::build_phase(uvm_phase phase);
    
22. uvm_object config_obj;
    
23. super.build_phase(phase);
    
24. if(cfg==null) begin
    
25. if(！uvm_config_db#(axi_config)::get(this,"","cfg",cfg))
    
26. `uvm_warning("NOCONFIG","Config not set for master agent, using default is_active field")
    
27. end
    
28. else is_active = cfg.master_config.is_active;
    
29. 
    
30. if(is_active==UVM_ACTIVE) begin
    
31. write_sequencer = axi_master_write_sequencer::type_id::create("write_sequencer",this);
    
32. write_driver= axi_master_write_driver::type_id::create("write_driver",this);
    
33. end
    
34. endfunction : build_phase
    
35. 
    
36. function void axi_master_agent::connect_phase(uvm_phase phase);
    
37. super.connect_phase(phase);
    
38. if(is_active==UVM_ACTIVE)
    
39. write_driver.seq_item_port.connect(write_sequencer.seq_item_export);
    
40. endfunction : connect_phase
    
41. 
    
42. function void axi_master_agent::update_config(input axi_config cfg);
    
43. if(is_active==UVM_ACTIVE) begin
    
44. write_sequencer.cfg=cfg;
    
45. end
    
46. endfunction : update_config

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axi_write_sequencer:

1. class axi_master_write_sequencer extends uvm_sequencer;
   
2. axi_config cfg;
   
3. 
   
4. `uvm_component_utils_begin(axi_master_write_sequencer)
   
5. `uvm_field_object(cfg, UVM_DEFAULT)
   
6. `uvm_component_utils_end
   
7. 
   
8. function new(string name, uvm_component parent);
   
9. super.new(name,parent);
   
10. endfunction : new
    
11. 
    
12. virtual function void build_phase(uvm_phase phase);
    
13. super.build_phase(phase);
    
14. if(cfg == null)
    
15. if(！uvm_config_db#(axi_config)::get(this,"","cfg",cfg))
    
16. `uvm_warning("NOCONFIG","apb_config not set for this component")
    
17. endfunction : build_phase
    
18. endclass : axi_master_write_sequencer

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axi_write_driver:

1. class axi_master_write_driver extends uvm_driver #(axi_transfer);
   
2. virtual axi_write_if vif;
   
3. axi_master_config cfg;
   
4. axi_transfer array_transfer[$];// use queue which size can be dynamically
   
5. 
   
6. `uvm_component_utils_begin(axi_master_write_driver)
   
7. `uvm_field_object(cfg,UVM_DEFAULT)
   
8. `uvm_component_utils_end
   
9. 
   
10. function new(string name,uvm_component parent);
    
11. super.new(name,parent);
    
12. endfunction : new
    
13. 
    
14. extern virtual function void build_phase(uvm_phase phase);
    
15. extern virtual function void connect_phase(uvm_phase phase);
    
16. extern virtual task run_phase(uvm_phase phase);
    
17. //extern virtual protected task get_and_drive();
    
18. extern virtual protected task reset();
    
19. extern virtual protected task drive();
    
20. extern virtual protected task drive_aw(axi_transfer trans);
    
21. extern virtual protected task drive_w(axi_transfer trans);
    
22. extern virtual protected task receive();
    
23. 
    
24. endclass : axi_master_write_driver
    
25. 
    
26. function void axi_master_write_driver::build_phase(uvm_phase phase);
    
27. super.build_phase(phase);
    
28. if(cfg == null)
    
29. if(！uvm_config_db#(axi_master_config)::get(this,"","cfg",cfg))
    
30. `uvm_error("NOCONFIG","axi_master_config not set for this component")
    
31. 
    
32. endfunction : build_phase
    
33. 
    
34. function void axi_master_write_driver::connect_phase(uvm_phase phase);
    
35. super.connect_phase(phase);
    
36. if(！uvm_config_db#(virtual axi_write_if)::get(this,"","vif",vif))
    
37. `uvm_error("NOVIF",{"virtual interface must be set for : ",get_full_name(),".vif"})
    
38. endfunction : connect_phase
    
39. .....
    
40. .....

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nc错误提示：
write_driver.seq_item_port.connect(write_sequencer.seq_item_export);
|
ncelab: *E,TYCMPAT (./axi_master_agent.sv,46|73): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'class uvm_port_base#(.IF(class uvm_sqr_if_base#(.T1(class axi_transfer),.T2(class axi_transfer))))' but found 'class uvm_seq_item_pull_imp#(.REQ(class uvm_sequence_item),.RSP(class uvm_sequence_item),.IMP(class uvm_sequencer#(.REQ(class uvm_sequence_item),.RSP(class uvm_sequence_item))))' instead).

01.class axi_master_write_sequencer extends uvm_sequencer #(axi_transfer);

顶楼上！你的sequencer后面没有加transaction类型。

谢谢楼上诸位！
这个问题终于解决了。

这个port 是UVM 自带的 port 么?

应该是uvm_sequencer和uvm_driver中自带的，写了自己的sequencer和driver可以直接使用的。

您好，我想问您一下，seq_item_port和seq_item_export是driver和sequencer自己已经定义好了，只需要在agent的connect——phase中完成连接就行了是吗?