求助 运行verdi命令 出现以下提示 是什么问题啊 求大侠详解

[root@localhost bin]# verdi
logDir = /usr/novas201004_tar/platform/LINUX/bin/verdiLog
vericom - A HDL Compiler, Release 2010.04 (Linux) 04/07/2010
Copyright (C) 1996 - 2010 by SpringSoft, Inc.
Usage: verdi [options] files
Options:
-2001Support Verilog IEEE 1364-2001 standard.
-2001genblkUse Verilog IEEE 1364-2001 naming style for generate
blocks(overrides other language options).
-2005Support IEEE 1364-2005 standard.
-amsSupport Verilog-AMS syntax.
-applogAppend the compile messages to log file (The
default mode is overwriting).
-autoendcelldefAutomatically appends `endcelldefine at the end of
a file if a matching `endcelldefine can not be
found for a declared `celldefine in the file.
-comment_transoff_regions -suboption | +suboption
Skip source code between translate_off/on pragmas
The suboptions are vendor names e.g. cadence, ikos,
mentor, novas, pragma, quickturn, synopsys, synthesis.
-cuname<cu name> Support ModelSim compilation-base compilation-unit mode
-cunitSupport Synopsys compilation-base compilation-unit mode
+define+<macro>The +define option is used to specify macros.
If the macro is also defined in your source code,
it will be overridden by this option.
-defineDefine a macro.
-errormax <number>
Specify the maximum number of errors to report. If the
errors exceed the number, the parser will skip reporting
the remaining errors.
-syntaxerrormax <number>
Specify the maximum number of syntax errors to stop parsing.
If the syntax errors exceed the number,
the parser will stop parsing the remaining files.
-extractRTLAutomatically recognizes the RTL storage elements.
The extracted storage elements will be saved into
the library.
-f <filename>Load an ASCII file containing design source files and
additional simulator options.
-helpDisplay this help menu.
-ignorekwd_config
Ignore the keyword of Verilog IEEE 1364-2001, "config".
-ignore_macro_redef
Suppress warning messages for re-defined macro(s).
+incdir+<directory_name>
Specify the search path for files used by the `include
statement.
-incdir <directory>
Specify an include directory.
-incsaveSpecify to decrease the compilation memory.
-LSpecify the library to search for packages.
+libext+<extension_name>
Used to specify the file extensions for Verilog library
files.
See also the -y option.

指令使用错误，没有按照规则使用

曾经遇到，正在学习中！

-2001genblk使用之后还是没有解决掉我的问题，在genblk中有调用其他CELL，仍然无法直接双击进入该CELL。学习中。

谁有verdi 相关的学习资料

thank you very much