微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 微电子和IC设计 > IC验证交流 > Help with "uvm_rand_send and uvm_rand_send_with"

Help with "uvm_rand_send and uvm_rand_send_with"

时间:10-02 整理:3721RD 点击:
Firstly, The computer can not support Chinese at present, So The post is in English! Don't blame on me!
A test(named test0) depends on the following things:
Tr---------seq0---------vseq0-------test0
The code has been described as bellow:
In Seq0's body(vseq0 has got some sameness):
Tr tr0;
`uvm_create(tr0);
tr0.some_static_variable=3'b001;
`uvm_rand_send_with(tr0, { tr0.rand_variable==int_value;});
But the int_value can not pass int the tr0 which diver has got?

when the rand variable's mode disable, uvm_rand_send can work after assignment.
How can I solve this problem using uvm_rand_send_with?
what is the detailed usage difference between uvm_rand_send and uvm_rand_send_with?
I cann't got them clearly now!
I need your help!
Thanks!

贴具体的代码上来。

uvm_rand_send(item) 和 uvm_rand_send_with(item, constraint) 只有一个区别前者包含item.randomize() with {} 后者则包含item.randomize() with {constraint}. 可能是你的constraint和item本身的constraint冲突了。

三楼说的应该是对的,约束冲突了。这两个约束应该和uvm_douvm_do_with的原理一样,前者无条件随机,后者有条件随机。

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top