IC 设计工程师
时间：10-02
整理：3721RD
点击：
我是IC猎头 这里有个IC设计工程师的职位
工作地点在上海
下面是JDJOB DESCRIPTION:
Design, evaluate and verify CMOS analog circuits.
Oversee layout and verification activities which include floor plan, LVS and DRC.
QUALIFICATION:
BSEE or MSEE.
Good fundamental in analysis and design of analog / mixed-signal circuits.
Experience in Verilog, AHDL and/or Matlab. Ability to do layout and provide verification/debugging guidance.
Solid knowledge of EDA design tools. (Analog artist, spectre, HSPICE and nc-verilog ...)
Familiar with Computer languages such as C, C++, perl.
工作地点在上海
下面是JDJOB DESCRIPTION:
Design, evaluate and verify CMOS analog circuits.
Oversee layout and verification activities which include floor plan, LVS and DRC.
QUALIFICATION:
BSEE or MSEE.
Good fundamental in analysis and design of analog / mixed-signal circuits.
Experience in Verilog, AHDL and/or Matlab. Ability to do layout and provide verification/debugging guidance.
Solid knowledge of EDA design tools. (Analog artist, spectre, HSPICE and nc-verilog ...)
Familiar with Computer languages such as C, C++, perl.
Experience in any of the following areas is preferred: PLL, high-speed I/O’s
有意向的兄弟姐妹们将你们的简历发送到下面这个邮箱,谢谢！
justin@genhr.com
DING YI GE ！
顶。