Verification in the trenches: A SystemC implementation of VMM1.2

翻译一篇vmmcentral上的文章，很多句子不知道如何翻译，欢迎指正．
原文：http://www.vmmcentral.org/vmarti ... entation-of-vmm1-2/
VMM1.2 class library is now also implemented in SystemC(VMM-SC).
现在VMM1.2的类库已经实现了SystemC(VMM-SC).
Will it help your project? Please take a few minutes to consider this, especially if you have been using or thinking about C/C++/SystemC models in your environment.
它能对你的项目有所帮助吗?请花上几分钟来考虑这个问题，尤其是你曾经在你的环境中使用过或者考虑过使用c/c++/Systemc模型．
Following are the some use cases that I have come across or can anticipate among our clients. With each use case, I have put down some thoughts on why VMM-SC may(or may not) be of any benefit. Do you agree?
下面是几个应用情景是来自我们的客户或者他们的预期．对于每个应用情景，我都记录下一些思考过程，为什么VMM-SC可能带来一些好处或者相反．不知道你赞成吗?
Use Case 1. Using SystemC as the primary verification language for unit level verification
情景１.使用SC做为主要的UT验证语言．
Many teams today use SystemC as their primary verification language for all unit and system-level tests. However, with the increasing popularity of SystemVerilog, they often adopt a hybrid model. They do use C++/SystemC as the primary language for testbench creation, but complement it using SystemVerilog language features for assertions, functional coverage analysis, and constrained random generation.
现在有很多team使用SC做他们UT和ST的主要验证语言．但是，随着SV的流行，他们经常采用混合模型．他们的确使用SC做为创建TB的主要语言，但是使用SV的一些features：断言、功能覆盖率分析和带约束的随机激励，做为补充．
Such teams often consider moving to SystemVerilog based environments, but are concerned about the reuse of their existing code, and cannot justify the ROI against the resources needed to make the transition to SystemVerilog completely. Ideally, they would like to have a multi-language solution that can mix and match SystemVerilog and SystemC components.
这些团队经常考虑把环境迁移到SV语言，但是考虑到重用已有的代码，and cannot justify the ROI(Return on investment) against the resources needed to make the transition to SystemVerilog completely.．最好的方法是他们可能采用一个混合了SV和SC组件的多语言解决方案．
For this class of users, VMM-SystemC can ease their adoption of a multi-language solution. First, they can create newer environments in VMM-SC, and encapsulate preexisting VIP within VMM-SC components using thin wrappers. Once transitioned to VMM-SC, they can easily interoperate with other VMM-SV based environments and components. As an added benefit of the SystemVerilog-SystemC interoperability, the VMM-SV applications such as RAL/Scoreboarding etc. can now be made available to the SystemC side.
对于这类用户，VMM-SC可以使他们采用多语言解决方案更为容易．首先，他们可以用VMM-SC创建新的环境，然后使用轻量级的wrappers把以前的VIP封装在VMM-SC组件中．一旦转换到VMM-SC，他们可以很容易的实现与基于VMM-SV的环境和组件互相操作．做为SV和SC互通的一个额外的好处，VMM-SV的RAL/Scoreboarding等在SC侧现在也是可见的．
Use Case 2. Using SystemC as the primary verification language for system-level verification
应用场景２．使用SC做ST的主要验证语言
Some teams decide to write their system level verification environments primarily in C/C++, as it is often used by the SW team or in the lab. Depending on the sophistication of these teams, these environments may range from being simple directed C testbenches to those that are highly sophisticated and use SystemC. Adopting VMM-SC as the system-level methodology can make it easier to cleanly pull in various environments and components by encapsulating them as VMM objects and making them work together taking advantage of VMM-SC support for phasing, TLM ports etc.
有的团队决定使用c/c++做为验证环境的主要语言，因为验证环境经常会提供给软件团队或者in the lab.基于这些混合的团队，这些环境可能简单的C环境变化到高度复杂的SC环境．采用VMM-SC做ST的验证方法可以把不同的环境和组件干净的封装在一起，使它们协同工作，同时利用VMM-SC支持phasing、TLM port等优点．
For this class of users, adopting VMM-SC as the top-level glue environment will be a big win.
对于这类用户，采用VMM-SC做为顶层的粘合环境将是巨大的成功．
Use Case 3. Planning to move to SystemVerilog and adopt industry standard practices.
应用场景３. 规划迁移到SV，采用业界标准的做法。
Often, teams are willing to start from scratch for new projects as they realize their existing environments have become outdated and simply cannot scale. With the maturity of SystemVerilog, they would likely adopt it as the primary HVL language of choice. However, they would still like to preserve a number of previously developed components.
团队往往愿意在新项目从头开始，因为他们认识到其现有的环境已过时而且不能扩展。
This is an ideal application for using VMM-SC. Pre-existing transactors can be converted to VMM-SC components by deriving them from vmm_xactor/vmm_unit classes(see 4.3 below). The new environment can now be written in VMM-SV, which can pull in the legacy components using VMM-SC/SV interoperability solution. All VMM features, such as cross language option setting, communicating transactions in a language agnostic way between source and target components using TLM, coordinated phasing etc. make the SystemVerilog adoption process much easier.
这是一个VMM-SC的理想用途．以前的transactors可以继承于vmm_xactor/vmm_unit类(见下面的4.3)从而转换为VMM-SC组件．新的环境可以用VMM-SC来写，这可以使用 VMM-SC/SV 互操作解决方案来引进遗留的组件。所有的VMM的特性，比如跨语言选项设置、使用TLM 在源和目标组件之间实现对语言透明的方式进行通信、协调phasing等，使得采用SV的过程更为容易．
Use Case 4.Using SystemC to develop ESL environments and reference models.
应用场景４.使用SC开发ESL模型和RM．
There are users who are primarily interested in creating models at various levels of abstraction. These models can be used in multiple applications, such as performance modeling and architectural exploration. In some cases, such models may not be of sufficient detail to use in functional verification.
有一些用户主要对创建不同抽象层次的模型感兴趣．这些模型可以用在各种应用中，比如性能模型和架构探索．在有的情况下，这些模型可能没有足够的细节来完成功能验证．
At the minimum, such models should be created using TLM2.0 ports to enable easy plug and play in ESL contexts. Adopting VMM-SC as the primary methodology for developing such components can be of benefit, since it offers a rich set of features that can help in controlling and coordinating the components, while maintaining strong interoperability with verification environments.
这些模型至少应该使用TLM2.0的端口使得更容易集成到ESL环境．采用VMM-SC做为开发这些组件的主要验证方法是有好处的．由于它提供了一组丰富的功能，可以帮助控制和协调各个组件，同时保持与验证环境组件有很强的互操作性。
So, to which one of these use cases do you belong? Any other use case that I missed?
那么你属于这里的哪种应用场景呢?还有其它我遗漏的应用场景吗?

小编辛苦了,顶

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