how to use "fine-grain process" in systemverilog

In systemverilog LRM, fine-grain process control is described as:
A process is a built-in class that allows one process to access and control another process once it has started.
Users can declare variables of type process and safely pass them through tasks or incorporate them into other
objects.
Objects of type process are created internally when processes are spawned. Users cannot create objects of type
process; attempts to call
new shall not create a new process, and instead result in an error. The process class
cannot be extended. Attempts to extend it shall result in a compilation error. Objects of type process are
unique; they become available for reuse once the underlying process terminates and all references to the object
are discarded.
and the exampe in LRM is:
task do_n_way( int N );
process job[1:N];
for ( int j = 1; j <= N; j++ )
fork
automatic int k = j;
begin job[j] = process::self(); ... ; end
join_none
for( int j = 1; j <= N; j++ )// wait for all processes to start
wait( job[j] ！= null );
job[1].await();// wait for first process to finish
for ( int k = 1; k <= N; k++ ) begin
if ( job[k].status ！= process::FINISHED )
job[k].kill();
end
endtask
I wrote my own code as following, but it did not work. I don't know why. Could any one can give me some suggetions?
module
...
...
process job_cpu;
initial
begin
c_flag = 0;
mem_value = 0;
#10ns;
$monitor("%t: mem_value = %0d ", $time,mem_value);
#10ns;
job_cpu = process::self();
cpu_main();
#10ns;
$finish;
end
...
...
endmodule
The simulation information is:
process job_cpu;
|
ncvlog: *E,NOIPRT (top.sv,14|14): Unrecognized declaration 'job_cpu' could be a spelling mistake [SystemVerilog].
It seems that the process is not recognized by the tool. Should I add some special statement before using the "process"?