Quartus 时序问题

Quartus 时序问题
大家好，我在用Quartus 做时序分析时遇到一个问题。
同一个寄存器、同一个时钟，在计算数据路径和时钟路径时，时钟的network delay不一样大（我认为应该是一样大的）。
求高人指点。
报告如下：
说明：osc_div8_clk是一个分频时钟（计数器实现），有门控
Info: Report Timing: Found 1 hold paths (1 violated).Worst case slack is -0.753
Info: -to_clock [get_clocks {osc_div8_clk}]
Info: Path #1: Hold slack is -0.753 (VIOLATED)
Info: ===================================================================
Info: From Node: tmcu_51a:UUT|pcgen:pcgen_i|pcgen_op:pcgen_op1|pc[3]
Info: To Node: tmcu_51a:UUT|pcgen:pcgen_i|pcgen_op:pcgen_op1|pc[3]
Info: Launch Clock : osc_div8_clk
Info: Latch Clock: osc_div8_clk
Info:
Info: Data Arrival Path:
Info:
Info: Total (ns)Incr (ns)TypeElement
Info: =================== =========================================
Info:0.0000.000launch edge time
Info:3.9293.929Rclock network delay
Info:4.0700.141uTcotmcu_51a:UUT|pcgen:pcgen_i|pcgen_op:pcgen_op1|pc[3]
Info:4.0700.000 RRCELLUUT|pcgen_i|pcgen_op1|pc[3]|regout
Info:4.0700.000 RRICUUT|pcgen_i|pcgen_op1|pc[3]~4234|datac
Info:4.2540.184 RRCELL UUT|pcgen_i|pcgen_op1|pc[3]~4234|combout
Info:4.2540.000 RRICUUT|pcgen_i|pcgen_op1|pc[3]|datain
Info:4.2960.042 RRCELLtmcu_51a:UUT|pcgen:pcgen_i|pcgen_op:pcgen_op1|pc[3]
Info:
Info: Data Required Path:
Info:
Info: Total (ns)Incr (ns)TypeElement
Info: =================== =========================================
Info:0.0000.000latch edge time
Info:4.8974.897Rclock network delay
Info:5.0490.152uThtmcu_51a:UUT|pcgen:pcgen_i|pcgen_op:pcgen_op1|pc[3]
Info:
Info: Data Arrival Time:4.296
Info: Data Required Time :5.049
Info: Slack:-0.753 (VIOLATED)
Info: ===================================================================

具体看看详细的报告，工具往往考虑的比较悲观，所以会有不同

不清楚，飘过

怎么好像没人解答