经典IC设计面试问题6
时间：10-02
整理：3721RD
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Whatis difference between Verilog full case and parallel case?
A"full" case statement is a case statement in which all possiblecase-expression binary patterns can be matched to a case item or to acase default. If a case statement does not include a case default and ifit is possible to find a binary case expression that does not match anyof the defined case items, the case statement is not "full."
A"parallel" case statement is a case statement in which it is onlypossible to match a case expression to one and only one case item. If itis possible to find a case expression that would match more than onecase item, the matching case items are called "overlapping" case itemsand the case statement is not "parallel."
A"full" case statement is a case statement in which all possiblecase-expression binary patterns can be matched to a case item or to acase default. If a case statement does not include a case default and ifit is possible to find a binary case expression that does not match anyof the defined case items, the case statement is not "full."
A"parallel" case statement is a case statement in which it is onlypossible to match a case expression to one and only one case item. If itis possible to find a case expression that would match more than onecase item, the matching case items are called "overlapping" case itemsand the case statement is not "parallel."
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