看看这个怎么做啊

1.
how few 4-input FPGA lookup tables (LUTs) can an 8:1 MUX function be implemented?

Just discuss in general, the answer is 3.
One for higher input, one for lower input, one for generation of control logic.
But both Xilinx and Altera have special LUT logic, their LUT offer unique function.
Perhaps 8-1 MUX would be implemented with fewer LUT.