哪位朋友能帮我检查下关于TAP CONTROLLER的代码？
时间：10-02
整理：3721RD
点击：
I am using Board FPGA Spartan3 and want to readback using JTAG TDO pin,the following is part of my source code (based on the TAP statemachine):
My question is that it seems that no data is clockedout of the TDO pin
process (JCLK)
begin
if rising_edge(JCLK) then
.........................
...............................
if (COUNTER = 17) then-- IDCODE Bit 5=0
TMS <= '0';
TDI <= '0';
end if;
if (COUNTER = 19) then --IDCODE Bit 6 (MSB)=0--Exit-IR1
TMS <= '1';--Update-IR--Select-DR-Scan
TDI <= '0';
end if;
if (COUNTER = 25) then --Capture-DR--Shift-DR
TMS <= '0';
TDI <= '0';
end if;
if (COUNTER = 29) then --
TMS <= '0';
DATAOUT_SIG(0) <= TDO;
end if;
if (COUNTER = 31) then
TMS <= '0';
DATAOUT_SIG(1) <= TDO;
end if;
TDO isdefinited in the entity as: in std_logic;--Test Data Out
and DATAOUT_SIG is signal of 32 bits width.
Can any one perhaps tell me where is wrong with this using style of readback IDCODE?
My question is that it seems that no data is clockedout of the TDO pin
process (JCLK)
begin
if rising_edge(JCLK) then
.........................
...............................
if (COUNTER = 17) then-- IDCODE Bit 5=0
TMS <= '0';
TDI <= '0';
end if;
if (COUNTER = 19) then --IDCODE Bit 6 (MSB)=0--Exit-IR1
TMS <= '1';--Update-IR--Select-DR-Scan
TDI <= '0';
end if;
if (COUNTER = 25) then --Capture-DR--Shift-DR
TMS <= '0';
TDI <= '0';
end if;
if (COUNTER = 29) then --
TMS <= '0';
DATAOUT_SIG(0) <= TDO;
end if;
if (COUNTER = 31) then
TMS <= '0';
DATAOUT_SIG(1) <= TDO;
end if;
TDO isdefinited in the entity as: in std_logic;--Test Data Out
and DATAOUT_SIG is signal of 32 bits width.
Can any one perhaps tell me where is wrong with this using style of readback IDCODE?
你到底要干什么?说的再清楚一些！
是JTAG的吗?
是的是JTAG；我想利用xilinx 的UG332中的TAP State Machine回读配置文件
但是编写的VHDL代码貌似没有将1其读出来，从TDO上读的都是0，不知道哪位大人有经验，能帮我看看可能出错在什么地方。
急等！
我的邮箱traeumerlingling@hotmail.com