请教一个VHDL的赋值语句
时间：10-02
整理：3721RD
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architecture xxx of key_file is
constant word: natural :=2;
constant bitn: natural :=16;
type reg_file_type is array (2**word-1 downto 0) of std_logic_vector(bitn-1 downto 0);
...
signal array_reg: reg_file_type;
...
begin
process (clk,reset)
begin
if (reset='1') then
array_reg(3) <= (other=>'0'); --这行赋值语句是怎么执行的，other代表什么意思?先谢过
...
elseif (clk'event and clk='1') then
...
end if;
end process;
....
end xxx
constant word: natural :=2;
constant bitn: natural :=16;
type reg_file_type is array (2**word-1 downto 0) of std_logic_vector(bitn-1 downto 0);
...
signal array_reg: reg_file_type;
...
begin
process (clk,reset)
begin
if (reset='1') then
array_reg(3) <= (other=>'0'); --这行赋值语句是怎么执行的，other代表什么意思?先谢过
...
elseif (clk'event and clk='1') then
...
end if;
end process;
....
end xxx
应该是others吧
意识是对所有的寄存器单元在复位情况下清零
全0的简洁写法
就是其它啊?vhdl的教程上都有
ones
zeros
others
这是赋值的简洁的写法嘛