我的分频设计（6.48M6.312M）

6.48M时钟为输入
9*(37clock + 1 gapped clock)+12(38 clock +1 gapped clock)
做9次每38个时钟扣一个脉冲，12次每39个时钟扣一个时钟脉冲，这样获得的带缺口的时钟就是6.312M时钟。
代码：
//this program is to divide clkock with frequency of 6.48M to frequency of 6.312M
module clock_deduct(clk_in,rst_n,clk_out);
input clk_in;
input rst_n;
output clk_out;
reg clk_out;
reg flag;
reg [3:0] counter9;
reg [3:0] counter12;
reg [5:0] counter38;//deduct one clock every 38 clock
reg [5:0] counter39;//deduct one clock every 39 clock
always@(posedge clk_in or negedge clk_in or negedge rst_n)
begin
if(rst_n==1'b0)
begin
flag<=1'b0;
counter9<=4'b0;
counter12<=4'b0;
counter38<=6'b0;
counter39<=6'b0;
clk_out<=1'b0;
end
else if(clk_in==1'b0)
clk_out<=1'b0;
else
begin
//----------------------------------------------
//deducting one clock every 38 clock for 9 times
//----------------------------------------------
if(flag==1'b0)
begin
if(counter38>=6'b100101)
begin
counter38<=6'b0;
if(counter9>=4'b1000)
begin
flag<=1'b1;
counter9<=4'b0;
counter38<=6'b0;
end
else
begin
counter9<=counter9+1'b1;
end
end
else
begin
counter38=counter38+6'b1;
//clk_out<=~clk_out;
clk_out<=clk_in;
end
end
//----------------------------------------------
//**********************************************
//----------------------------------------------
//----------------------------------------------
//deducting one clock every 39 clock for 12 times
//----------------------------------------------
else if(flag==1'b1)
begin
if(counter39>=6'b100110)
begin
counter39<=6'b0;
if(counter12>=4'b1011)
begin
flag<=1'b0;
counter12<=4'b0;
counter39<=6'b0;
end
else
begin
counter12<=counter12+1'b1;
end
end
else
begin
counter39=counter39+6'b1;
//clk_out<=~clk_out;
clk_out<=clk_in;
end
end
//----------------------------------------------
//**********************************************
//----------------------------------------------
end

end
endmodule

收下了，回去研究研究！