大家看看那里错了 vhdl 程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity speed is
port (fp,reset:in std_logic;
speed0,speed1:buffer std_logic_vector(3 downto 0);
speed2,speed3:buffer std_logic_vector(3 downto 0));
end speed;
architecture behave of speed is
signal c1,c2,c3:std_logic;
begin
spd0:process(reset,fp)
begin
if reset= '1' then
speed0<="0000"; speed1<="0000";
speed2<="0000"; speed3<="0000";
c1<='0'; c2<='0'; c3<='0';
elsif (fp'event and fp='1') then
if speed0="1001" then
speed0<="0000"; c1<='1';
else speed0<=speed0+1; c1<='0';
end if;
end if;
end process spd0;
spd1:process(c1)
begin
if (c1'event and c1='1') then
if speed1="1001" then
speed1<="0000"; c2<='1';
else speed1<=speed1+1; c2<='0';
end if;
end if;
end process spd1;
spd2:process(c2)
begin
if (c2'event and c2='1') then
if speed2="1001" then
speed2<="0000"; c3<='1';
else speed2<= speed2+1; c3<='0';
end if;
end if;
end process spd2;
spd3: process (c3)
begin
if (c3'event and c3='1') then
if speed3="1001" then
speed3<="0000";
else speed3<=speed3+1;
end if;
end if;
end process spd3;
end behave;

仿真说是有多个源 不知道什么原因 请那位高手检查修改以下
谢谢

哈哈，程序写的太不好读了。

你的错误是这个原因：举其中一个例子：

你在block sp0中 对speed1 进行了赋值；
然后你又在spd1中对 speed1 又进行了赋值；

所以你编译的时候会出错：speed1有多个源。

修改方法： 把所有对speed1赋值的操作放在一个process 里面。

spd0:process(reset,fp)
begin
if reset= '1' then
speed0<="0000"; speed1<="0000";
speed2<="0000"; speed3<="0000";
c1<='0'; c2<='0'; c3<='0';
elsif (fp'event and fp='1') then
if speed0="1001" then
speed0<="0000"; c1<='1';
else speed0<=speed0+1; c1<='0';
end if;
end if;
end process spd0;

speed1, speed2, speed3在其它process中再次赋值，可以把此处的reset复位分别加到其它process中