i2c写程序
时间：10-02
整理：3721RD
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_write is
port(
clk,
nreset:in std_logic;
d:in std_logic_vector(7 downto 0);
start,
stop,
read,
write: in std_logic;
-- load,
--shift: out std_logic;
dout: out std_logic;
SCL,
SDA: out std_logic
);
end i2c_write;
architecture arc_i2c_core of i2c_write is
component p2s_altera is
port(
clk,
clkih,
stld,
ser: in std_logic;
d :in std_logic_vector(0 to 7);
q,
nq: out std_logic
);
end component p2s_altera;
--signal for i2c_core
signal sclo,sdao:std_logic;
signal din:std_logic;
signaldcnt:unsigned(3 downto 0);
signal iload,ishift:std_logic;
type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d,ack_a,ack_b,ack_c,ack_d,nack_a,nack_b,nack_c,nack_d);
--state:00000000010001000011001000010100110001110100001001 0101001011 01100 01101 01110 01111 10000 10001 10010 10011 10100 101011011010111
signal state:cmds;
--signal for p2s_altera
signaliclkih,istld, iser:std_logic;
signal do :std_logic;
signal flag: std_logic;
signal iflag:std_logic;
--signal for shift_control process
type shift_type is(s1,s2,s3);
signal shift_state: shift_type;
begin
-- generateparallel to serial
shift: p2s_altera port map(clk,iclkih,istld,iser,d,din,do);
dout<=din;
-- generate i2c_core data transfer
p1 : process (nreset,clk,state,start,read,write,din)
--variable nxt_state : cmds;
--variable icmd_ack, ibusy, store_sda : std_logic;
--variable itxd : std_logic;
--variable iload,ishift:std_logic;
variable iscl,isda:std_logic;
variable idcnt:unsigned(3 downto 0);
begin
-- generate regs
if (nReset = '0' )then
state <= idle;
scl<='1';
sda<='1';
dcnt<="1000";
elsif (clk'event and clk = '1') then
SCL<=sclo;
SDA<=sdao;
dcnt<=idcnt;
case state is
when idle=>
iscl:='0';
isda:='0';
if(start='1')then
state<=start_a;
elsif stop='1' then
state<=stop_a;
elsif read='1'then
idcnt:="1000";
ishift<='1';
state<=rd_a;
else
idcnt:="1000";
iload<='1';
state<=wr_a;
end if;
-- start
when start_a =>
iscl := '0'; -- keep SCL in same state (for repeated start)
isda := '1'; -- set SDA high
state <= start_b;
when start_b =>
iscl:='1';
isda:='1';
state <= start_c;
when start_c =>
iscl:='1';
isda:='0';
state <= start_d;
when start_d =>
iscl:='0';
isda:='0';
-- icmd_ack := '1';
--if core_ack='1' then
if read='1' then
idcnt:="1000";
ishift<='1';
state<=rd_a;
else
idcnt:="1000";
iload<='1';
state<=wr_a;
end if;
-- stop
when stop_a =>
iscl:='0';
isda:='0';
state <= stop_b;
when stop_b =>
iscl:='1';
isda:='0';
state <= stop_c;
when stop_c =>
iscl:='1';
isda:='1';
--when stop_d =>
state <= idle;
-- read
when rd_a =>
iscl:='0';
isda:='1';--sda;
state <= rd_b;
when rd_b =>
iscl:='1';
isda:='0';--sda;
state <= rd_c;
when rd_c =>
iscl:='1';
isda:='1';--sda;
state <=rd_d;
when rd_d =>
iscl:='0';
isda:='0';--sda;
idcnt:=idcnt-1;
if stop='1' then
state<=nack_a;
elsif idcnt=0then
state <= ack_a;
else
state<=rd_a;
end if;
-- write
when wr_a =>
iscl:='0';
isda:=din;
iflag<='0';
state <= wr_b;
when wr_b =>
iscl:='1';
isda:=din;
iflag<='0';
state <= wr_c;
when wr_c =>
iscl:='1';
isda:=din;
iflag<='0';
state <= wr_d;
when wr_d =>
iscl:='0';
isda:=din;
iflag<='1';
idcnt:=idcnt-1;
if(idcnt=0)then
state <= ack_a;
iflag<='0';
else
state<=wr_a;
end if;
when ack_a=>
iscl:='0';
isda:='0';
state <= ack_b;
when ack_b=>
isda:='0';
iscl:='1';
state <= ack_c;
when ack_c=>
iscl:='1';
state <= ack_d;
when ack_d=>
isda:='0';
iscl:='0';
ifstop='1' then
state<=stop_a;
elsif(write='1') then
state<=wr_a;
idcnt:="1000";
iload<='1';
elsif(read='1') then
state<=rd_a;
idcnt:="1000";
ishift<='1';
else
state<=idle;
end if;
when nack_a=>
iscl:='0';
isda:='1';
state <= nack_b;
when nack_b=>
isda:='1';
iscl:='1';
state <= nack_c;
when nack_c=>
isda:='1';
iscl:='0';
state <= nack_d;
when nack_d=>
isda:='1';
state<=stop_a;
end case;
sclo<=iscl;
sdao<=isda;
end if;
end process p1;
shift_control: process(clk,iflag,dcnt)
begin
if(clk'event and clk='1') then
case shift_state is
when s1=>
iclkih<='0';
istld<='0';
iser<='0';
shift_state<=s2;
when s2=>
iclkih<='1';
istld<='1';
iser<='1';
if iflag='1'then
if(dcnt=8) then
shift_state<=s1;
elsif dcnt=0then
shift_state<=s2;
else
shift_state<=s3;
end if;
else
shift_state<=s2;
end if;
when s3=>
iclkih<='0';
istld<='1';
iser<='1';
shift_state<=s2;
end case;
end if;
end process shift_control;
end architecture arc_i2c_core;
LIBRARY altera;
USE altera.maxplus2.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity p2s_altera is
port(
clk,
clkih,
stld,
ser: in std_logic;
d :in std_logic_vector(0 to 7);
q,
nq: out std_logic
);
end p2s_altera;
architecture arc_p2s2 of p2s_altera is
begin
u1: a_74165bport map (clk, clkih, stld, ser, d,q,nq);
end arc_p2s2;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_write is
port(
clk,
nreset:in std_logic;
d:in std_logic_vector(7 downto 0);
start,
stop,
read,
write: in std_logic;
-- load,
--shift: out std_logic;
dout: out std_logic;
SCL,
SDA: out std_logic
);
end i2c_write;
architecture arc_i2c_core of i2c_write is
component p2s_altera is
port(
clk,
clkih,
stld,
ser: in std_logic;
d :in std_logic_vector(0 to 7);
q,
nq: out std_logic
);
end component p2s_altera;
--signal for i2c_core
signal sclo,sdao:std_logic;
signal din:std_logic;
signaldcnt:unsigned(3 downto 0);
signal iload,ishift:std_logic;
type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d,ack_a,ack_b,ack_c,ack_d,nack_a,nack_b,nack_c,nack_d);
--state:00000000010001000011001000010100110001110100001001 0101001011 01100 01101 01110 01111 10000 10001 10010 10011 10100 101011011010111
signal state:cmds;
--signal for p2s_altera
signaliclkih,istld, iser:std_logic;
signal do :std_logic;
signal flag: std_logic;
signal iflag:std_logic;
--signal for shift_control process
type shift_type is(s1,s2,s3);
signal shift_state: shift_type;
begin
-- generateparallel to serial
shift: p2s_altera port map(clk,iclkih,istld,iser,d,din,do);
dout<=din;
-- generate i2c_core data transfer
p1 : process (nreset,clk,state,start,read,write,din)
--variable nxt_state : cmds;
--variable icmd_ack, ibusy, store_sda : std_logic;
--variable itxd : std_logic;
--variable iload,ishift:std_logic;
variable iscl,isda:std_logic;
variable idcnt:unsigned(3 downto 0);
begin
-- generate regs
if (nReset = '0' )then
state <= idle;
scl<='1';
sda<='1';
dcnt<="1000";
elsif (clk'event and clk = '1') then
SCL<=sclo;
SDA<=sdao;
dcnt<=idcnt;
case state is
when idle=>
iscl:='0';
isda:='0';
if(start='1')then
state<=start_a;
elsif stop='1' then
state<=stop_a;
elsif read='1'then
idcnt:="1000";
ishift<='1';
state<=rd_a;
else
idcnt:="1000";
iload<='1';
state<=wr_a;
end if;
-- start
when start_a =>
iscl := '0'; -- keep SCL in same state (for repeated start)
isda := '1'; -- set SDA high
state <= start_b;
when start_b =>
iscl:='1';
isda:='1';
state <= start_c;
when start_c =>
iscl:='1';
isda:='0';
state <= start_d;
when start_d =>
iscl:='0';
isda:='0';
-- icmd_ack := '1';
--if core_ack='1' then
if read='1' then
idcnt:="1000";
ishift<='1';
state<=rd_a;
else
idcnt:="1000";
iload<='1';
state<=wr_a;
end if;
-- stop
when stop_a =>
iscl:='0';
isda:='0';
state <= stop_b;
when stop_b =>
iscl:='1';
isda:='0';
state <= stop_c;
when stop_c =>
iscl:='1';
isda:='1';
--when stop_d =>
state <= idle;
-- read
when rd_a =>
iscl:='0';
isda:='1';--sda;
state <= rd_b;
when rd_b =>
iscl:='1';
isda:='0';--sda;
state <= rd_c;
when rd_c =>
iscl:='1';
isda:='1';--sda;
state <=rd_d;
when rd_d =>
iscl:='0';
isda:='0';--sda;
idcnt:=idcnt-1;
if stop='1' then
state<=nack_a;
elsif idcnt=0then
state <= ack_a;
else
state<=rd_a;
end if;
-- write
when wr_a =>
iscl:='0';
isda:=din;
iflag<='0';
state <= wr_b;
when wr_b =>
iscl:='1';
isda:=din;
iflag<='0';
state <= wr_c;
when wr_c =>
iscl:='1';
isda:=din;
iflag<='0';
state <= wr_d;
when wr_d =>
iscl:='0';
isda:=din;
iflag<='1';
idcnt:=idcnt-1;
if(idcnt=0)then
state <= ack_a;
iflag<='0';
else
state<=wr_a;
end if;
when ack_a=>
iscl:='0';
isda:='0';
state <= ack_b;
when ack_b=>
isda:='0';
iscl:='1';
state <= ack_c;
when ack_c=>
iscl:='1';
state <= ack_d;
when ack_d=>
isda:='0';
iscl:='0';
ifstop='1' then
state<=stop_a;
elsif(write='1') then
state<=wr_a;
idcnt:="1000";
iload<='1';
elsif(read='1') then
state<=rd_a;
idcnt:="1000";
ishift<='1';
else
state<=idle;
end if;
when nack_a=>
iscl:='0';
isda:='1';
state <= nack_b;
when nack_b=>
isda:='1';
iscl:='1';
state <= nack_c;
when nack_c=>
isda:='1';
iscl:='0';
state <= nack_d;
when nack_d=>
isda:='1';
state<=stop_a;
end case;
sclo<=iscl;
sdao<=isda;
end if;
end process p1;
shift_control: process(clk,iflag,dcnt)
begin
if(clk'event and clk='1') then
case shift_state is
when s1=>
iclkih<='0';
istld<='0';
iser<='0';
shift_state<=s2;
when s2=>
iclkih<='1';
istld<='1';
iser<='1';
if iflag='1'then
if(dcnt=8) then
shift_state<=s1;
elsif dcnt=0then
shift_state<=s2;
else
shift_state<=s3;
end if;
else
shift_state<=s2;
end if;
when s3=>
iclkih<='0';
istld<='1';
iser<='1';
shift_state<=s2;
end case;
end if;
end process shift_control;
end architecture arc_i2c_core;
LIBRARY altera;
USE altera.maxplus2.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity p2s_altera is
port(
clk,
clkih,
stld,
ser: in std_logic;
d :in std_logic_vector(0 to 7);
q,
nq: out std_logic
);
end p2s_altera;
architecture arc_p2s2 of p2s_altera is
begin
u1: a_74165bport map (clk, clkih, stld, ser, d,q,nq);
end arc_p2s2;
[转帖]i2c写程序
green_pine兄怎么不在你自己的坛子里（ copyleft)帖东西?
我看你很少在那里！
[转帖]i2c写程序
刚才坏了你财路是不是。?
可不要这么小气。
[转帖]i2c写程序
要价不低阿
[转帖]i2c写程序
太黑了,呵呵
[转帖]i2c写程序
我的空间快到期了
[转帖]i2c写程序
因为这里正在设计iic丫，所以要高点，嘿嘿
[转帖]i2c写程序
为什么sda不是双向的
[转帖]i2c写程序
k！
[转帖]i2c写程序
好像不能用的
我有i2c verilog（国外网址下载的），改天我免费传上来。
[转帖]i2c写程序
gui
[转帖]i2c写程序
贵了点吧，iic的资料有很多的！
[转帖]i2c写程序
太黑了
[转帖]i2c写程序
太黑了吧?
10元也许适合似的.
[转帖]i2c写程序
免费的东东才好！
[转帖]i2c写程序
真的太太贵了
[转帖]i2c写程序
还是转贴呢！是不是你写的阿?
还是在OPENCORE上下的阿?
我按照你写的做了一下编译，可是出来却有这样的错误：
Error: Node instance "u1" instantiates undefined entity "a_74165b"
请问这是怎么回事啊?
太黑了,呵呵
这个程序我也有，可是仿真出来的结果怎么是错误的呢，请高手指教一下，是不是我哪的设置有问题啊?
要价?什么价?怎么我看不到?