谁能回答我的问题？

请看下面的两段代码有什么区别?
感觉读写地址的数据类型不一样，但下面的代码是非同步读而上面的代码是同步读RAM,那位能告诉我为甚么?
Example 6–12. VHDL Single-Clock Synchronous RAM Without Read-Through-Write Behavior
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ram IS
PORT (
clock: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to 31;
read_address: IN INTEGER RANGE 0 to 31;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END ram;
ARCHITECTURE rtl OF ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL ram_block: MEM;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
q <= ram_block(read_address);
-- VHDL semantics imply that q doesn't get data
-- in this clock cycle
END IF;
END PROCESS;
END rtl;
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Example 6–18. VHDL Single-Clock Synchronous RAM with Asynchronous Read Address
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram IS
GENERIC (
ADDRESS_WIDTH: integer := 4;
DATA_WIDTH: integer := 8
);
PORT (
clock: IN std_logic;
data: IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
write_address IN STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 DOWNTO 0);
read_address IN STD_LOGIC_VECTOR(ADDRESS_WIDTH - 1 DOWNTO 0);
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0)
);
END ram;
ARCHITECTURE rtl OF ram IS
TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1
DOWNTO 0);
SIGNAL ram_block: RAM;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(TO_INTEGER(UNSIGNED(write_address))) <= data;
END IF;
q <= ram_block(TO_INTEGER(UNSIGNED(read_address)));
END IF;
END PROCESS;
END rtl;

感觉是一样的
仿真一下看看

哈哈。这是ALTERA手册上的一段代码！

没看出有什么区别！

没区别啊

有点难啊 刚看了VHDL 基础 不好~和