请问怎么样在cpld中使用全局时钟？
时间：10-02
整理：3721RD
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在cpld中使用全局时钟，看介绍要使用BUFG的。在Verilog HDL中如下定义：
input clk_in;
wire clk_tmp,clk_buf;
IBUF GBUFa(.O(clk_tmp),.I(clk_in));
BUFG GBUFb(.O(clk_buf),.I(clk_tmp));
在assign package pins里把clk_in定义到GCLK3上了，但在XST时还是报错：
Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:455 - logical net 'clk_tmp' has multiple driver(s):
pin O on block GBUFa with type IBUF,
pin PAD on block clk_tmp with type PAD
WARNING:NgdBuild:463 - input pad net 'clk_tmp' has an illegal input buffer
ERROR:NgdBuild:925 - input net 'clk_tmp' is connected to the incorrect side of
buffer(s):
pin O on block GBUFa with type IBUF
求教，BUFG的正确用法，谢谢各位了。
input clk_in;
wire clk_tmp,clk_buf;
IBUF GBUFa(.O(clk_tmp),.I(clk_in));
BUFG GBUFb(.O(clk_buf),.I(clk_tmp));
在assign package pins里把clk_in定义到GCLK3上了，但在XST时还是报错：
Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:455 - logical net 'clk_tmp' has multiple driver(s):
pin O on block GBUFa with type IBUF,
pin PAD on block clk_tmp with type PAD
WARNING:NgdBuild:463 - input pad net 'clk_tmp' has an illegal input buffer
ERROR:NgdBuild:925 - input net 'clk_tmp' is connected to the incorrect side of
buffer(s):
pin O on block GBUFa with type IBUF
求教，BUFG的正确用法，谢谢各位了。
哪位高手指点一下,谢谢