大侠们，来帮帮忙！

Started process "Fit".
Release 6.2i - CPLD Optimizer/Partitioner G.28
Copyright (c) 1995-2004 Xilinx, Inc.All rights reserved.
Considering device XC9536-10-VQ44.
Flattening design..
Timing optimization
Timespec driven global resource optimizationAll paths with TIMESPECs have been optimized.
Timing driven global resource optimization
General global resource optimization........
Timespec driven global resource optimization
Re-checking device resources ...
Mapping a total of 31 equations into 2 function blocks...........................ERROR:Cpld:892 - Cannot place signal SHELL1_MUSM2.delay_key2. Consider reducing
the collapsing input limit or the product term limit to prevent the fitter
from creating high input and/or high product term functions.
See the fitter report for details.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
ERROR: Fit failed
Reason:
Process "Fit" did not complete.
是不是我选用的片子不合适呀

大侠们，来帮帮忙！
你选的芯片放不下你的设计。