实在不明白哪里出错,请指教!谢谢
时间:10-02
整理:3721RD
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module MUL(clk,nRESET,Startpulse,Donepulse, A,B,p);
output [15:0] p;
output Donepulse;
input clk;
input nRESET;
input Startpulse;
input [7:0] A,B;
reg Donepulse;
reg [15:0] p;
reg [7:0] A,B;
reg [14:0] p1,c1;
reg [12:0] p2;
reg [10:0] p3,c2;
reg [8:0]p4;
reg[14:0] A_temp;
reg[13:0] A_temp1;
reg[12:0] A_temp2;
reg[11:0] A_temp3;
reg[10:0] A_temp4;
reg[9:0] A_temp5;
reg[8:0] A_temp6;
reg[7:0] A_temp7;
function [7:0] and81;
input [7:0] operand;
input sel;
reg [7:0] operand;
reg sel;
and81=(sel)?(operand):8'b00000000;
endfunction
always @(posedge clk or negedge nRESET)
begin
if (!nRESET)
begin
p=0;
A=0;
B=0;
Donepulse=0;
A_temp=8'b0;
A_temp1=8'b0;
A_temp2=8'b0;
A_temp3=3'b0;
A_temp4=8'b0;
A_temp5=8'b0;
A_temp6=8'b0;
A_temp7=8'b0;
end
else
begin
if(Startpulse)
begin
A_temp[14:7]=and81(A,B[7]);
A_temp[6:0]=7'b0000000;
A_temp1[13:6]=and81(A,B[6]);
A_temp1[5:0]=6'b000000;
A_temp2[12:5]=and81(A,B[5]);
A_temp2[4:0]=5'b00000;
A_temp3[11:4]=and81(A,B[4]);
A_temp3[3:0]=4'b0000;
A_temp4[10:3]=and81(A,B[3]);
A_temp4[2:0]=3'b000;
A_temp5[9:2]=and81(A,B[2]);
A_temp5[1:0]=2'b00;
A_temp6[8:1]=and81(A,B[1]);
A_temp6[0]=0;
A_temp7=and81(A,B[0]);
p1=A_temp+A_temp1;
p2=A_temp2+A_temp3;
p3=A_temp4+A_temp5;
p4=A_temp6+A_temp7;
c1=p1+p2;
c2=p3+p4;
p=c1+c2;
Donepulse=1;
end
end
end
endmodule
算法采用加法器树乘法器,Quartus2 3.0编译的时候出两个错
Error: Net A[7] at MIXJXK.v(84) is already driven by input port A[7], and cann
ot be driven by another signal
Error: Port A[7] is declared at MIXJXK.v(8)
output [15:0] p;
output Donepulse;
input clk;
input nRESET;
input Startpulse;
input [7:0] A,B;
reg Donepulse;
reg [15:0] p;
reg [7:0] A,B;
reg [14:0] p1,c1;
reg [12:0] p2;
reg [10:0] p3,c2;
reg [8:0]p4;
reg[14:0] A_temp;
reg[13:0] A_temp1;
reg[12:0] A_temp2;
reg[11:0] A_temp3;
reg[10:0] A_temp4;
reg[9:0] A_temp5;
reg[8:0] A_temp6;
reg[7:0] A_temp7;
function [7:0] and81;
input [7:0] operand;
input sel;
reg [7:0] operand;
reg sel;
and81=(sel)?(operand):8'b00000000;
endfunction
always @(posedge clk or negedge nRESET)
begin
if (!nRESET)
begin
p=0;
A=0;
B=0;
Donepulse=0;
A_temp=8'b0;
A_temp1=8'b0;
A_temp2=8'b0;
A_temp3=3'b0;
A_temp4=8'b0;
A_temp5=8'b0;
A_temp6=8'b0;
A_temp7=8'b0;
end
else
begin
if(Startpulse)
begin
A_temp[14:7]=and81(A,B[7]);
A_temp[6:0]=7'b0000000;
A_temp1[13:6]=and81(A,B[6]);
A_temp1[5:0]=6'b000000;
A_temp2[12:5]=and81(A,B[5]);
A_temp2[4:0]=5'b00000;
A_temp3[11:4]=and81(A,B[4]);
A_temp3[3:0]=4'b0000;
A_temp4[10:3]=and81(A,B[3]);
A_temp4[2:0]=3'b000;
A_temp5[9:2]=and81(A,B[2]);
A_temp5[1:0]=2'b00;
A_temp6[8:1]=and81(A,B[1]);
A_temp6[0]=0;
A_temp7=and81(A,B[0]);
p1=A_temp+A_temp1;
p2=A_temp2+A_temp3;
p3=A_temp4+A_temp5;
p4=A_temp6+A_temp7;
c1=p1+p2;
c2=p3+p4;
p=c1+c2;
Donepulse=1;
end
end
end
endmodule
算法采用加法器树乘法器,Quartus2 3.0编译的时候出两个错
Error: Net A[7] at MIXJXK.v(84) is already driven by input port A[7], and cann
ot be driven by another signal
Error: Port A[7] is declared at MIXJXK.v(8)
实在不明白哪里出错,请指教!谢谢
怎么输入定义成reg类型,还要在always块里面赋值,不明白.输入就该是wire类型呀.
实在不明白哪里出错,请指教!谢谢
请贴出你的测试分支,这样才可以准确判断和分析。
实在不明白哪里出错,请指教!谢谢
hitlzh的分析是对的
实在不明白哪里出错,请指教!谢谢
除了hitlzh说的,另外在always时序模块里还是用非阻塞赋值<=比较好吧!