帮忙解决一下
时间:10-02
整理:3721RD
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我再ise集成中调用是这样:
# vsim -L simprims_ver -lib work -t 1ps +maxdelays testbench glbl
# Loading work.testbench
# Loading work.statecontrol
# Loading D:/ise/Modeltech_se/win32/../simprims_ver.X_BUF
# Loading D:/ise/Modeltech_se/win32/../simprims_ver.X_INV
。
单独在modelsim中调用就这样错了:
vsim -sdfmax /controltest/UUT=E:/fengli/my_pci/sim2/statecontrol_timesim.sdf work.controltest
# vsim -sdfmax /controltest/UUT=E:/fengli/my_pci/sim2/statecontrol_timesim.sdf work.controltest
# Loading work.controltest
# Loading work.statecontrol
# ** Error: (vsim-3033) E:/fengli/my_pci/sim2/statecontrol_timesim.v(312): Instantiation of 'X_BUF' failed. The design unit was not found.
#Region: /controltest/UUT
#Searched libraries:
#work
# ** Error: (vsim-3033) E:/fengli/my_pci/sim2/statecontrol_timesim.v(316): Instantiation of 'X_BUF' failed. The design unit was not found.
#Region: /controltest/UUT
#Searched libraries:
#work
。
急坏了!
# vsim -L simprims_ver -lib work -t 1ps +maxdelays testbench glbl
# Loading work.testbench
# Loading work.statecontrol
# Loading D:/ise/Modeltech_se/win32/../simprims_ver.X_BUF
# Loading D:/ise/Modeltech_se/win32/../simprims_ver.X_INV
。
单独在modelsim中调用就这样错了:
vsim -sdfmax /controltest/UUT=E:/fengli/my_pci/sim2/statecontrol_timesim.sdf work.controltest
# vsim -sdfmax /controltest/UUT=E:/fengli/my_pci/sim2/statecontrol_timesim.sdf work.controltest
# Loading work.controltest
# Loading work.statecontrol
# ** Error: (vsim-3033) E:/fengli/my_pci/sim2/statecontrol_timesim.v(312): Instantiation of 'X_BUF' failed. The design unit was not found.
#Region: /controltest/UUT
#Searched libraries:
#work
# ** Error: (vsim-3033) E:/fengli/my_pci/sim2/statecontrol_timesim.v(316): Instantiation of 'X_BUF' failed. The design unit was not found.
#Region: /controltest/UUT
#Searched libraries:
#work
。
急坏了!
帮忙解决一下
加上-L simprims_ver试试看呢?
帮忙解决一下
不行,,,是路径问题么?你注意看一下我单独调用时的路径,和集成环境中调用的路径,,
帮忙解决一下
我觉得问题还是在这:
#Searched libraries:
#work
除了搜索work库,还应该搜索simprims_ver库。
要不你添上绝对路径: -L D:/ise/Modeltech_se/win32/../simprims_ver 试试看
帮忙解决一下
嗯,,,对了,,谢谢,,,嘿嘿,,
帮忙解决一下
Error: (vsim-3043) F:/modelsim/test1/controltest.v(56): Unresolved reference to 'S_IDLE' in UUT.S_IDLE.
#Region: /controltest
你再看一下这个问题,,,因为我的test文件中有:defparam UUT.S_IDLE = 2'b00;
帮忙解决一下
如果你在位号为uut的器件里定义了s_idle的参数那应该没什么问题才对,这句话写的位置对不对?