有无用过marvell处理器的，startburst如何处理？
时间：12-13
整理：3721RD
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marvell 88f6281处理器关于ddr2接口的信号startburst 和startburst_in的描述只有
如下一段话，没看懂这个信号应该布多长？感觉好像应该和DDR的DQ信号一样长，但看了
一个别人的pcb，startburst 和startburst_in加起来2000mil，但是DQ线却>3000mil。
有没有用过的，指点一下。
The front-end logic of the SDRAM controller is responsible for correct sampling of the double datarate data with M_DQS signals, as well as the packing of data from 16-bit DDR to 32-bit SDR. A 16-bit DDR read data is latched via the received DQS (shifted by ? cycle, via the delay line). The first 16-bits are sampled with the rising edge of DQS, and the next 64-bits with the falling edge of DQS.
To meet the DDR SDRAM AC specification, packed 32-bit read data cannot simply be sampled with the internal SDRAM controller clock. The exact sample point depends on class latency, silicon process, and board topology. The controller drives a M_STARTBURSTn signal, as an envelope of the read data phase. Route this signal on the board all the way to the SDRAM, and back to the controller as M_STARTBURST_INn feedback. This signal is used as a reference for proper data sample.
如下一段话，没看懂这个信号应该布多长？感觉好像应该和DDR的DQ信号一样长，但看了
一个别人的pcb，startburst 和startburst_in加起来2000mil，但是DQ线却>3000mil。
有没有用过的，指点一下。
The front-end logic of the SDRAM controller is responsible for correct sampling of the double datarate data with M_DQS signals, as well as the packing of data from 16-bit DDR to 32-bit SDR. A 16-bit DDR read data is latched via the received DQS (shifted by ? cycle, via the delay line). The first 16-bits are sampled with the rising edge of DQS, and the next 64-bits with the falling edge of DQS.
To meet the DDR SDRAM AC specification, packed 32-bit read data cannot simply be sampled with the internal SDRAM controller clock. The exact sample point depends on class latency, silicon process, and board topology. The controller drives a M_STARTBURSTn signal, as an envelope of the read data phase. Route this signal on the board all the way to the SDRAM, and back to the controller as M_STARTBURST_INn feedback. This signal is used as a reference for proper data sample.
从内容上看，应该跟数据线一样长。不管别人怎么布线，
你把所有的线都尽量等长好了。
关键是有两片DDR芯片，DQ的长度不一致，不知道应该按哪个。
用marvell的东西真窝火，手册不全，还要不到，自称是代理商的也没有。
pcb走线延时很小的，不用很精确等长
才2片DDR，不是很容易等长吗？
1. cpu - DDR1 - DDR2
2.
DDR1
CPU
DDR2
这个哪个代理商说的？